Outline Computer Organization Devices Interrupts Computer architecture Central processing unit Instruction execution Devices Interrupts Please pick up Homework #1 from the front desk if you have not got a copy

Review: System Overview 12/1/2018 COP4610

Stored Program Computers and Electronic Devices Pattern Variable Program Stored Program Device Jacquard Loom Fixed Electronic Device 12/1/2018 COP4610

Jacquard Loom 12/1/2018 COP4610

von Neumann Architecture 12/1/2018 COP4610

The von Neumann Architecture – cont. A von Neumann architecture consists of A central processing unit made up of ALU and control unit A primary memory unit I/O devices Buses to interconnect the other components 12/1/2018 COP4610

von Neumann Architecture – cont. The crucial difference between computers and other electronic devices is the variable program 12/1/2018 COP4610

Central Processing Unit Datapath ALU – Arithmetic/Logic Unit Registers General-purpose registers Control registers Communication paths between them Control Controls the data flow and operations of ALU 12/1/2018 COP4610

S1 bus Dest bus S2 bus Control unit ALU A R0, r1,... (registers) C B ia(PC) psw... MAR IR MDR MAR memory address register MDR memory data register IR instruction register Memory

ALU Unit 12/1/2018 COP4610

Memory Organization 12/1/2018 COP4610

Instruction Execution Instruction fetch (IF) MAR  PC; IR  M[MAR] Instruction Decode (ID) A  Rs1; B  Rs2; PC  PC + 4 Execution (EXE) Depends on the instruction Memory Access (MEM) Write-back (WB) 12/1/2018 COP4610

Arithmetic Instruction Example r3  r1 + r2 IF: MAR  PC; IR  M[MAR] ID: A  r1; B  r2; PC  PC + 4 EXE: ALUoutput  A + B MEM: WB: r3  ALUoutput 12/1/2018 COP4610

S1 bus Dest bus S2 bus Control unit ALU A R0, r1,... (registers) C B ia(PC) psw... MAR IR MDR MAR memory address register MDR memory data register IR instruction register Memory

Memory Instruction Example load 30(r1), r2 IF: MAR  PC; IR  M[MAR] ID: A  r1; PC  PC + 4 EXE: MAR  A + #30 MEM: MDR  M[MAR] WB: r2  MDR 12/1/2018 COP4610

S1 bus Dest bus S2 bus Control unit ALU A R0, r1,... (registers) C B ia(PC) psw... MAR IR MDR MAR memory address register MDR memory data register IR instruction register Memory

Branch/jump Instruction Example bnez r1, -16 IF: MAR  PC; IR  M[MAR] ID: A  r1; PC  PC + 4 EXE: ALUoutput  PC + #-16; cond  (A op 0) MEM: if (cond) PC  ALUoutput WB: r1 = 100 r4 = 0 r3 = 1 L1: r4 = r4 + r3 r3 = r3 + 2 r1 = r1-1 if (r1!=0) goto L1 // Outside loop // r4 ? 12/1/2018 COP4610

S1 bus Dest bus S2 bus Control unit ALU A R0, r1,... (registers) C B ia(PC) psw... MAR IR MDR MAR memory address register MDR memory data register IR instruction register Memory

Devices I/O devices are used to place data into primary memory and to store its contents on a more permanent medium Logic to control detailed operation Physical device itself Each device uses a device controller to connect it to the computer’s address and data bus Many types of I/O devices 12/1/2018 COP4610

Devices – cont. Device manager Program to manage device controller Application Program Device Controller Device Software in the CPU Abstract I/O Machine Device manager Program to manage device controller Supervisor mode software 12/1/2018 COP4610

Devices – cont. General device characteristics Block-oriented devices Character-oriented devices Input devices Output devices Storage devices Communication devices 12/1/2018 COP4610

Device Controllers A hardware component to control the detailed operations of a device Interface between controllers and devices Interface between software and the controller Through controller’s registers 12/1/2018 COP4610

Device Controllers – cont. Command Status Data 0 Data 1 Data n-1 Logic busy done Error code . . . busy done 0 0 idle 0 1 finished 1 0 working 1 1 (undefined) 12/1/2018 COP4610

Communication Between CPU and Devices Through busy-done flag Called polling A busy-waiting implementation Not effective 12/1/2018 COP4610

Polling I/O busy done Software Hardware … // Start the device While(busy == 1) wait(); // Device I/O complete done = 0; while((busy == 0) && (done == 1)) // Do the I/O operation busy = 1; busy done Software Hardware 12/1/2018 COP4610

Polling I/O – cont. It introduces busy-waiting while(deviceNo.busy || deviceNo.done) <waiting>; deviceNo.data[0] = <value to write> deviceNo.command = WRITE; while(deviceNo.busy) <waiting>; deviceNo.done = TRUE; It introduces busy-waiting The CPU is busy, but is effectively waiting Devices are much slower than CPU CPU waits while device operates Would like to multiplex CPU to a different process while I/O is in process 12/1/2018 COP4610

A More Efficient Approach When a process is waiting for its I/O to be completed, it would be more effective if we can let another process to run to fully utilize the CPU It requires a way for the device to inform the CPU when it has just completed I/O 12/1/2018 COP4610

Better Utilization of CPU Device … Ready Processes I/O Operation Uses CPU 12/1/2018 COP4610

Interrupts 12/1/2018 COP4610

Interrupt Handling – cont. 12/1/2018 COP4610

Interrupts – cont. program Interrupt handler interrupt 12/1/2018 COP4610

Interrupts – cont. An interrupt is an immediate (asynchronous) transfer of control caused by an event in the system to handle real-time events and running-time errors Interrupt can be either software or hardware I/O device request (Hardware) System call (software) Signal (software) Page fault (software) Arithmetic overflow Memory-protection violation Power failure 12/1/2018 COP4610

Interrupts – cont. Causes of interrupts: System call (syscall instruction) Timer expires (value of timer register reaches 0) I/O completed Program performed an illegal operation: Divide by zero Address out of bounds while in user mode Segmentation fault 12/1/2018 COP4610

Synchronous vs. Asynchronous Events occur at the same place every time the program is executed with the same data and memory Can be predicted Asynchronous Caused by devices external to the processor or memory 12/1/2018 COP4610

Interrupt Handling When an interrupt occurs, the following steps are taken Save current program state Context switch to save all the general and status registers of the interrupted process Find out the interrupt source Go to the interrupt handler 12/1/2018 COP4610

Interrupt Handling – cont. Problem when two or more devices finish during the same instruction cycle Race condition between interrupts 12/1/2018 COP4610

A Race Condition saveProcessorState() { for(i=0; i<NumberOfRegisters; i++) memory[K+i] = R[i]; for(i=0; i<NumberOfStatusRegisters; i++) memory[K+NumberOfRegisters+i] = StatusRegister[i]; } 12/1/2018 COP4610

Interrupt Handling – cont. Race condition between interrupts Interrupt-enabled flag 12/1/2018 COP4610

Trap Instruction 12/1/2018 COP4610

Signal in UNIX Signal can be an asynchronous or synchronous event For example, CTRL-C generates SIGINT Divide-by-zero is a synchronous event Signals sent to a process Are handled by the operating system on behalf of the running process The program can change the default action taken by the operating system for a particular signal Function signal does not handle any signal by itself 12/1/2018 COP4610

Memory-mapped I/O Instructions to access device controller’s registers Special I/O instructions Memory-mapped I/O 12/1/2018 COP4610

Addressing Devices Primary Memory Primary Memory Memory Addresses Device Addresses Device n-1 Device n-1 12/1/2018 COP4610

Intel System Initialization RAM Boot Prog ROM Loader Power Up Boot Device POST OS BIOS CMOS … Hardware Process Data Flow 12/1/2018 COP4610

Bootstrapping Bootstrap loader (“boot sector”) Primary Memory PC IR 1 Fetch Unit Decode Unit Execute Unit 0000100 … PC IR BIOS loader 0x0000100 0x0001000 Primary Memory 12/1/2018 COP4610

Bootstrapping – cont. Bootstrap loader (“boot sector”) Loader 1 0x0000100 2 BIOS loader 0x0001000 Fetch Unit Decode Unit Execute Unit 0001000 … PC IR 0x0008000 Loader Primary Memory 12/1/2018 COP4610

Bootstrapping Bootstrap loader (“boot sector”) Loader OS 1 0x0000100 2 BIOS loader 0x0001000 Fetch Unit Decode Unit Execute Unit 0008000 … PC IR 0x0008000 Loader 3 0x000A000 OS Primary Memory 12/1/2018 COP4610

Bootstrapping – cont. Bootstrap loader (“boot sector”) Loader OS Primary Memory Loader OS 1 2 3 4. Initialize hardware 5. Create user environment 6. … Fetch Unit Decode Unit Execute Unit 000A000 … PC IR BIOS loader 0x0000100 0x0001000 0x0008000 0x000A000 12/1/2018 COP4610

A Bootstrap Loader Program FIXED_LOC: // Bootstrap loader entry point load R1, =0 load R2, =LENGTH_OF_TARGET // The next instruction is really more like // a procedure call than a machine instruction // It copies a block from FIXED_DISK_ADDRESS // to BUFFER_ADDRESS read BOOT_DISK, BUFFER_ADDRESS loop: load R3, [BUFFER_ADDRESS, R1] store R3, [FIXED_DEST, R1] incr R1 bleq R1, R2, loop br FIXED_DEST 12/1/2018 COP4610

A Pipelined Function Unit Operand 1 Function Unit Result Operand 2 (a) Monolithic Unit Operand 1 Result Operand 2 (b) Pipelined Unit 12/1/2018 COP4610

A SIMD Machine … (a) Conventional Architecture (b) SIMD Architecture ALU Control Unit … (b) SIMD Architecture ALU Control Unit (a) Conventional Architecture 12/1/2018 COP4610

Multiprocessor Machines Shared memory multiprocessors Distributed memory multiprocessors 12/1/2018 COP4610

Summary The von Neumann architecture is used in most computers To manage I/O devices or effectively, interrupts are used Interrupt handling involves hardware and software support There are also machines which use a different architecture Array processors; multiprocessors 12/1/2018 COP4610