Sungho Kang Yonsei University Fault Simulation Sungho Kang Yonsei University

Outline Introduction Parallel Deductive Concurrent PPSFP Critical Path Tracing PROOFS PARIS Fault Sampling Statistical Fault Analysis Hardware Acceleration Hierarchical Fault Simulation Conclusion

Fault Simulation Introduction

Application Evaluating Test Vectors Generating Tests Introduction Evaluating Test Vectors Generating Tests Constructing Fault Dictionaries Analyzing Circuits under Presence of Faults

Application: Evaluating Test Vectors Introduction Fault Coverage Ratio of the number of faults detected by a test vectors to the number of total faults Represents approximation of defect coverage which is the probability that test vectors detect physical defects

Application: Evaluating Test Vectors Introduction Quality of Test Y : Yield DL: Defect Level d : defect coverage DL = 1 - Y 1-d Consider a 0.5 yield process To achieve 0.01 defect level, 99% coverage is required To achieve 80% coverage, 0.2 defect level

Application : Generating Tests Introduction Use fault simulation first For remaining faults, use deterministic algorithm

Application : Fault Dictionaries Introduction Fault Dictionary Stores the output response of every faulty circuit corresponding to a fault Stores the signature Computing response before testing Post-test Diagnosis Isolating a reduced set of plausible fault Simulating only these faults to identify the actual fault

Application : Analyzing Circuits Introduction Important in high-reliability systems A fault can induce races and hazards not present in the fault-free circuit A faulty circuit may oscillate or enter a deadlock state A fault can inhibit the proper initialization of a sequential circuit A fault can transform a combinational circuit into a sequential circuit or a synchronous into asynchronous

Basic Fault Simulation Introduction Fault Specification Fault Insertion Fault Propagation Fault Detection Post Processing

Fault Specification Introduction This is the activity which determines which faults and fault types will be modeled during simulation Normally the total set of faults to be considered is determined before any simulation takes place and is the first fault-related activity to occur Later certain techniques or heuristics can be used to reduce this fault set but the resulting fault set is a subset of the one that is initially

Fault Insertion Introduction Fault insertion in a fault simulation system is very analogous to the process of physical fault insertion for a fabricated machine It can also be termed a fault transformation, where the fault free network is transformed into a network which contains a physical defect or fault This process can occur once for a given fault, before fault simulation begins, or it can occur numerous times during a fault simulation process, for each fault that is being modeled

Fault Propagation Introduction A fault simulation system obviously must have the ability to propagate the effects of a fault

Fault Propagation (a) (b) (c) Fault is propagated Introduction (a) Fault is propagated (b) Fault is propagated through multiple paths (c) Fault is blocked

Fault Detection Introduction A fault simulation system must have the ability to determine when a fault has become observable at some given point or primary output of the object network Whether this activity takes place concurrently with the actual simulation or at the end of a fault simulation pass depends on other attributes of the simulator

Postprocessing Introduction The fault simulation of a given digital network can result in a large amount of data which the user must interpret and efficiently utilize In an attempt to aid the user in this process one of the last activities which a fault simulation system performs is to organize the resulting data in a way which makes it most amenable to the user This activity can actually take place as a stand alone process

Methods General Combinational Synchronous Sequential Serial Parallel Introduction General Serial Parallel Deductive Concurrent Combinational PPSFP Trace-based Combined Synchronous Sequential PROOFS PARIS

Serial Fault Simulation Parallel Simulation Simplest Consider fault one at a time No special fault simulator is required Can handle any types of faults Impractical Excessive amount of CPU time

Parallel Fault Simulation Parallel Simulation A good circuit and w faulty circuits are simulated simultaneously passes are required w : number of bits of the host machine g f1 f2 f3 f4 f5 f6 f7 a 1 1 1 1 a c b 1 1 1 1 1 1 b a·b 1 1 a 1 1 1 1 1 1

Parallel Fault Simulation Parallel Simulation One good machine

Fault Insertion Parallel Simulation 2 input AND

3 Valued Logic Encoding 2 input AND C=AB 1 = 10 0 = 00 X = 01 Parallel Simulation Encoding 1 = 10 0 = 00 X = 01 Not used = 11 2 input AND C=AB C1 = A1&B1 C2 = A2&B2 | A1&B2 | A2&B1

3 Valued Logic Parallel Simulation 2 input AND Evaluation

3 Valued Logic Encoding 2 input AND C=AB 2 input OR C=A+B NOT C=~A Parallel Simulation Encoding 0 = 01 1 = 10 X = 00 Not used = 11 2 input AND C=AB C1 = A1&B1 C2 = A2|B2 2 input OR C=A+B C1 = A1|B1 C2 = A2&B2 NOT C=~A C1 = A2 C2 = A1

Parallel Fault Simulation Parallel Simulation 3 Valued Logic : Mask MASK1 MASK2 0 0 No fault 0 1 Stuck-at-X 1 0 Stuck-at-0 1 1 Stuck-at-1 V1 = V1 MASK1’ + MASK2 V2 = V2 MASK1’ + MASK2 MASK1’

Fault Insertion Parallel Simulation 3 Valued Logic

Fault Insertion Set appropriate bit to 0 to 1 Fault masks Parallel Simulation Set appropriate bit to 0 to 1 Fault masks s-a-0: 111···10111···1: AND to value vector s-a-1: 00000···010···0: OR to value vector    a/1 b/1 c/0 c/1 A 1 1 B 1 1 1 1 1 1 m1(a/1) 1 Insert a/1 A1 1 1 1 A + m1(a/1) B1 1 1 1 1 1 1 C 1 1 A1 · B1 m0(c/0) 1 1 1 1 1 1 1 C1 1 C · m0(c/0) Faults simulated: ,,, a/1, b/1, c/0, c/1 m1(c/1) 1 Insert c/1 C2 1 1 C + m1(c/1)

3 Values Coding a a1 a0 1 U b b1 b0 1 U Logic operations: c = a·b Parallel Simulation Coding a a1 a0 1 U b b1 b0 1 U Logic operations: c = a·b c0 = a0 + b0 , c1 = a1 · b1 c 1 U 1 c0 1 c1 Other logic operations: c = a + b: c0 = a0 · b0 , c1 = a1 + b1 c = a : c0 = a1 , c1 = a0 Vector-pairs for logic values

Example c = a · b C1 = A0 + B0 = 1 1 1 0 C0 = A1 · B1 = 0 0 0 0 c/0 Parallel Simulation c = a · b C1 = A0 + B0 = 1 1 1 0 C0 = A1 · B1 = 0 0 0 0 c/0 c/1  A = 1 U U B = U A1 = 1 A0 = 1 B1 = B0 = 1 1 1

Fault Insertion Two masks per fault Parallel Simulation Two masks per fault m1(c/0) = 1 0 1 1; m0(c/0) = 0 1 0 0 m1(c/1) = 0 0 1 0; m0(c/1) = 1 1 0 1 Inserting c/0 c1 = c1 · m1(c/0), c0 = c0 + m0(c/0) Inserting c/1 c1 = c1 + m1(c/1), c0 = c0 · m0(c/1)

Parallel Fault Simulation Parallel Simulation Apply all vectors against one group of faults generate a fault list for all faults which are not detected for all patterns initialize the circuit choose a pattern which is not simulated select 31 faults which are not detected fault simulation with fault insertion fault detection end

Parallel Fault Simulation Parallel Simulation Apply one vector against all faults generate a fault list for all patterns choose a pattern which is not simulated initialize the circuit for all faults which are not detected select 31 faults which are not detected fault simulation with fault insertion fault detection end

Parallel Fault Simulation Parallel Simulation Possible to reduce the number of passes by simulating several independent faults simultaneously Independent faults can be simulated in the same bit Least upper bound is p number of POs F/(Wp) passes are required Limitations Requires Boolean equation models Logical operations only Complex for multi-valued logic Cannot use selective trace Fault dropping is not effective

Deductive Fault Simulation Simulates a good circuit and deduce all faulty circuits Only a few faults may produce values different from fault-free values Keep fault-free values and differences Parallel 0 1 2 3 4 5 6 7 1 1 1 1 0 1 0 1 Deductive {4,6}

Deductive Fault Simulation AND (a) a=b=1 (b) a=0, b=1 (c) a=b=0

Deductive Fault Simulation N input AND

Fault List Deductive Set of single faults that will complement the fault-free(true) value at a line Example: let A,B,C be fault lists at a,b,c, respectively a=0, A={1,3,4,6} b=1, B={3,6} What is C? C= A – B ={1,4}

Fault List Deductive Set of single faults that will complement the fault-free value at a line Example 2 input AND C=AB where A=0 and B=1 fault list of A = {1,3,4,6} fault list of B = {4,6} fault list of C= A-B = {1,3}

Gate Evaluation Determine good value at the gate output Deductive Determine good value at the gate output Determine fault list on the gate output Fault effect that propagate through gate Local fault to be inserted Notation Lower case letters : lines Upper case letters : fault lists on corresponding lines

Fault Propagation Deductive Deduce output fault list of a gate from input true values and fault list B=A a=1,b=0,c=0;d=0 D=B∩C – A D=A – B – C

Fault Propagation Through Primitive Gates Deductive Fault Propagation Through Primitive Gates c = controlling logic value of gate I = set of gate inputs C = set of gate inputs with true value = c z = gate output Lj = fault list on j If C = , then Lz = ∪jI Lj Else Lz = {∩j C Lj} – {∪i ( I – C ) Li}

Correction of Computed Fault List Deductive Correction of Computed Fault List Let a=0, A={α,β,c/1} b=1, B =  But, c/1 can’t be detected. So c/1 must be deleted After computing this fault list propagating to a line j, it must be checked for consistency If j =vj, = Lj – { j/vj } where is the corrected fault list, and Lj is the propagated fault list a c b

Deductive Fault Simulation When a fault list is computed, new one should be compared to old one More complex for feedbacks More complex for memory elements Repeat until stabilization Consider as a primitive

Deductive Fault Simulation Fault Storage Linked List Sequential Table Characteristic Vector

Example Example V1 = <a,b,d> = <0,1,0> Deductive Example V1 = <a,b,d> = <0,1,0> V2 = <a,b,d> = <0,1,1> Vector 1 a=0, { a/1 }; b=1, { b/0 }; d=0, { d/1 } c=1, { b/0, c/0 }; h=1,{ b/0, h/0 } e=1; E = ( A–H ) ∪ { e/0 }={ a/1, e/0 } f=0; F=(D–C) ∪ {f/1}={ d/1, f/1 } g=1; G=(E-F) ∪ {g/0}={ a/1, e/0, g/0 } a h e b c g f d

Example Vector 2 d=1, { d/0 } f=1; F=(C∪D) ∪ { f/0 } Deductive Vector 2 d=1, { d/0 } f=1; F=(C∪D) ∪ { f/0 } ={ b/0, c/0, d/0, f/0 } g=1; G=(E ∩ F) ∪ { g/0 }={ g/0 } a h e b c g f d

Example Deductive

Unknown Values Fault-free values : { 0,1,U } Faulty values : { 0,1,U } Deductive Fault-free values : { 0,1,U } Faulty values : { 0,1,U } Cannot represent with one fault list Approximation : Star faults Example a=1, A={ , * } With fault , a = 0 With fault , a = U  *  A : not known whether   A or   A

Information Loss with Star Faults Deductive Fault-free / faulty values - true value, fault list Assume a single fault  0/0 0,{} 0/1 0,{} 0/U 0,{*} 1/0 1,{} 1/1 1,{} 1/U 1,{*} U/0 U,{} U/1 U,{} U/U U,{} Unable to distinguish U/0,U/1,U/U: potential loss of information

Deductive Fault Simulation Advantages Fast Large number of faults Limitations Compatible only in part with functional level modeling Cannot take full advantage of selective trace Inaccuracy in some cases : unknown values Large memory requirements

Concurrent Fault Simulation Simulates good circuit and simulates only faulty circuits that are different from the one in good circuit Concurrent Fault List Directly applicable to functional level modeling Requires lots of memory

Concurrent Fault Simulation Explicit simulation of fault-free and faulty circuits as in serial Keep differences between faulty and fault-free as in deductive Deductive Concurrent 0,{r} a a c 1 b 0,{r} 1,{,} b 1   1 r

Algorithm Features Separate fault-free and faulty events Concurrent Separate fault-free and faulty events Independent evaluations Keep only faulty states that are different from fault free states: delete others (convergence) Create faulty states when they become different from fault-free (divergence)

Fault Insertion Concurrent Faults in each gate inserted in its CFL(Concurrent Fault List) at the beginning of simulation Local faults not deleted during convergence operation Special evaluation of faulty gates Initialization Simulate after fault insertion

Fault List Changes 1/0 good event propagated to a Concurrent 1/0 good event propagated to a 0/1 good event on a(0) also updates the input a() to 0 Once evaluating the output c(0), 0/1 good event on c(0) occurs 1/0 good event a 1 c e b 1 1 d 1 a1 1 1 c1 1 1  1 d1 1 1 1  1  1 1

Fault List Changes Update c(0) to 1 Fanout processing : Concurrent Update c(0) to 1 Fanout processing : Propagate the changed value 1 on c(0) and the newly visible value 0 on c(a1) to fanout Updates the input c(0) to 1 1/0 good event a1 newly visible a c 1 e b 1 1 d 1 1 a1 1 c1 1  1 d1 1 1 1  1  1 1

Fault List Changes Concurrent a1 becomes newly visible on the fanout gate : Divergence Copy all values from the good state of the corresponding gate Change the input c(a1) to 0 obtained by fanout processing Don’t converge the faulty state(c1) because c1 is a local fault

Fault List Changes Updates the input c(d1) to 1 Concurrent Updates the input c(d1) to 1 Once evaluating the output e(d1), 1/0 faulty event on e(d1) occurs Updates input c() to 1 Once evaluating the output e(), 1/0 faulty event on e() occurs 1/0 event in circuit d1 1/0 event in circuit  a c 1 1 e b 1 1 d 1 a1 1 a1 1 1 1  c1 1 1 d1 1 1  1

Convergence When state of faulty gate = state of good gate, Concurrent When state of faulty gate = state of good gate, delete state of faulty gate When gate output is updated If good state changed Compare all faulty with good ( after faulty update ) If only faulty states changed Compare changed faulty with good

Divergence Concurrent Create a faulty gate when its state becomes different from good state Done at fanout propagation Copy good state : change fan-ins that are different

Fanout Processing Propagate changed values Concurrent Propagate changed values Propagate newly visible values If good value changed, propagate it to gates in CFL of fanout gate(s) that are not in CFL of source gate

Fanout Processing A C A C     B B    Concurrent b(0): 0/1 Good event c(0): 0/1 Good event b(): newly visible: 0 c():  newly visible: 0 A C A C 1 1 a 0 1 c 0 1 0 1 0 1 0 1 b 1 1     1 0 1 B B  1 1 1 1  

Example a(0) : The good event 0/1 arrived on a(0) Concurrent G1 0/1 G2 a(0) : The good event 0/1 arrived on a(0) a() : Newly visible: 0 Update the output of G1 to 0 Now what happen ? a 1/0 e 1 1 b 1 1  1  1  f 1 1  1 1 a/1 1 a/1 1 G3 1 c 1 d 1  

Example Fanout processing : fanout data preparation Concurrent Fanout processing : fanout data preparation e(0): Good event 1/0 e(): Newly visible: 1 G1 a 0/1 G2 1/0 e 1 1 b 1 g Convergence 1  1  1 f Newly visible  1 1  1 Nothing to do 1 a/1 1 a/1 G3 1 c 1 d 1  

Example Fanout processing : Fanout data propagation Concurrent Fanout processing : Fanout data propagation Propagate the good event 1/0 to the input e(0) of G1 Propagate the good event 1/0 to the faulty inputs of G1: e(), e(), e(a/1) Divergence G2() Update the output g(0) to 1 Convergence G2() Convergence G2(a/1) G1 a 0/1 G2 1/0 e 1/0 1 b 1 g 1 a/1  1 1  1 f Divergence 1 1  Need to update 1/0  1 G3 1 c 1 1 d a/1 1 1   1

Concurrent Fault Simulation

Concurrent Fault Simulation

Features of Three Methods Comparison Parallel and deductive Logic expression only Other expression  Boolean Values  binary encoding CHDL statements  Boolean expressions Concurrent No restrictions on : element types values delay models

Comparison of Three Methods Values Elements Storage Delays Fault-dropping Par binary logic min / fixed restricted not useful Conc any max / variable yes Ded med / variable

PPSFP Parallel Pattern Single Fault Propagation Advantage Limitation Parallel pattern evaluation Advantage Simple and efficient. Selective trace: Single fault propagation Signals whose values are identical in the fault free circuit and the faulty circuit are not recalculated. Limitation Fails to consider the timing environment. Since it does not work like event driven simulation, it is limited to devices which are combinational. Faults which can produce races or hazards, which can make a circuit oscillate, and which can change a combinational circuit into a sequential one, require additional considerations.

PPSFP Example Pattern 001 or 011 can detect the fault Fault Free Circuit Evaluation Consider C s-a-0 fault Pattern 001 or 011 can detect the fault

PPSFP Example Consider B s-a-0 fault After D evaluation, simulation stops since the result is the same as the fault free evaluation Try other patterns

PPSFP Algorithm for all patterns choose 32 patterns which are not simulated simulate a good circuit record the values for all faults which are not detected select a fault simulate a circuit under this fault if the value is the same as the value in the previous fault-free simulation after fault insertion stop simulation else continue detect a fault at primary outputs if the fault is detected delete the fault from the fault list end

Trace Based Simulation Crithical Path Restrict explicit fault simulation to stems Backtracking inside FFRs(fanout free regions) If no fault in an FFR propagates to its stem, the stem fault need not be simulated If all faults in an FFR have been detected, the FFR is dropped

Critical Path Tracing Crithical Path A line L has a critical value v in the test T iff T detects the fault L s-a-v A line with a critical value in T is said to be critical in T A gate input is sensitive if complementing its value changes the value of the gate output If only one input j has the controlling value (c) of the gate then j is sensitive If all inputs have c’ then all inputs are sensitive Otherwise no input is sensitive If a gate output is critical then its sensitive inputs, if any, are also critical

Critical Path Tracing Crithical Path Let T be a test that activates fault f in a single output combinational circuit Let y be a line with level ly, sensitized to f by T If every path sensitized to f either goes through y or does not reach any line with level greater than ly, then y is a capture line (surrogate line) of f in the test T

Surrogate Lines The stem or PO at the output of an FFR : Crithical Path The stem or PO at the output of an FFR : the surrogate line of the FFR D f4 B f2 A E f1 f5 C f3 F f6

Fanout Free Regions Surrogate Lines : L, N, T, S, CO Crithical Path CO Y X L L3 C1 X1 Y1 Q R L2 Y2 X2 L1 T1 C11 N1 C12 N2 T2 V S Surrogate Lines : L, N, T, S, CO

Fanout Free Regions Surrogate Lines : L, N, T, S Crithical Path U T N Y X L C1 X1 Y1 Q R L2 Y2 X2 L1 T1 C11 N1 C12 N2 T2 V S Surrogate Lines : L, N, T, S

Fanout Free Regions Surrogate Lines : L, CO Crithical Path Q L Y X C12

Criticality Crithical Path If test t detects a fault on l, line l is said to be critical in t Pls POs t X l

Stem Criticality Crithical Path A line l is stem-critical in a test t, if t propagates a fault on l to its surrogate line  X l

Critical Path Tracing A gate i propagates fault effects iff Crithical Path A gate i propagates fault effects iff either fault effects arrive only on sensitive inputs of i or fault effects arrive on all the nonsensitive inputs of I with controlling value and only on these inputs Propagation through AND 1  1  1

Determine Criticality & Stem-Criticality Backtrace Crithical Path Determine Criticality & Stem-Criticality Example of backtracing in a fanout free circuit 1 B A C  (a) 1   A 1 1    1 1   1  B 1 1 (b)  C 1 

Examples: Stem-Criticality Crithical Path Examples: Stem-Criticality C1 1 C11 X2 1 1 L1 C12 X Q R T1 U X1 L T S N N1 V 1 T2 1 1 Y1 1 Y L2 Y2 1 N2 T3 CO L3 1

Stem Criticality Crithical Path C1 1 C11 X2 1 1 L1 C12 X Q R T1 U X1 L U X1 L T S N N1 V 1 1 Y1 T2 1 1 Y L2 Y2 1 N2

Stem Criticality Crithical Path C1 1 X2 1 C12 1 X L1 Q X1 L N T N1 1 L N T N1 1 Y1 L2 Y R 1 T3 1 CO Y2 1 L3

Critical Path Tracing Crithical Path A test T detects the fault f iff all the capture lines of f in T are critical in T It is sufficient to propagate the fault effects only to the first capture line of the stem fault Then the stem is critical iff the capture line is critical

Criticality of Surrogate Lines Crithical Path C1 1 C11 X2 1 1 C12 X L1 Q R T1 U X1 L T  S    N N1 V 1 T2 1 Y1 1 1 Y L2 Y2 1 N2 T3 CO  L3 1  Critical Surrogate Lines: L, N, T, S, CO

Criticality of Surrogate Lines Crithical Path C1 1 C11 X2 1 1 L1 C12 X Q R T1 U X1 L T  S    N N1 V 1 T2 1 1 Y1 1 Y L2 Y2 1 N2  Critical Surrogate Lines: L, N, T, S

Criticality of Surrogate Lines Crithical Path 1 X2 C1 1 C12 1 X L1 Q X1 L N T N1 1 Y1 L2 Y R 1 T3 1  CO Y2 1 L3  Critical Surrogate Lines: CO

Criticality and Stem Criticality Crithical Path A line l is critical in a test t, iff the line l is stem-critical and its stem is critical in the test t t Pls POs x l

Criticality of Lines      Crithical Path C1 1 C11 X2 1 1 L1 C12 X Q R U X1 L T  S    N N1 V 1 T2 1 1 Y1 1 Y L2 Y2 1 N2 T3 CO  L3 1

Criticality of Lines     Crithical Path C1 1 C11 X2 1 1 L1 C12 X Q U X1 L T  S    N N1 V 1 T2 1 1 Y1 1 Y L2 Y2 1 N2

Criticality of Lines  Crithical Path 1 X2 C1 1 C12 1 X L1 Q X1 L N T L N T N1 1 Y1 L2 Y R 1 T3 1  CO Y2 1 L3

Critical Path Tracing Crithical Path Sometimes critical path tracing may not identify all the faults detected by a test This may occur in a test that propagates the effect of a fault on multiple paths that reconverge at a gate without sensitive inputs in T It is likely detected in other tests Example Effects of J/0

Trace Based Algorithm 1. True Value Simulation Crithical Path 1. True Value Simulation 2. Backtrace through FFRs (Identify stem-critical lines) 3. Simulate stem faults (Identify critical stems) 4. Backtrace through FFRs with critical stems (Identify critical lines) f4 f5 f6 f2 f3 f1 A B C D E F

Parallel Pattern Trace Based Crithical Path 1. True Value Simulation 2. Backtrace through FFRs (Identify stem-critical lines) 3. Simulate stem faults (Identify critical stems) 4. Backtrace through FFRs with critical stems (Identity critical lines) *All steps done in parallel pattern f4 f5 f6 f2 f3 f1 A B C D E F

Critical Path Tracing Algorithm for every primary output z Crithical Path Algorithm for every primary output z stems_to_check = NULL extend(z) while stem_to_check != NULL j = the highest level stem in stems_to_check remove j from stems_to_check if critical(j) extend(j) end

Critical Path Tracing FFR Crithical Path FFR stops at FFR inputs and collects all the stems reached in the set stems_to_check extend(j) mark j as critical if j is fanout branch add stem(j) to stems_to_check else critical(j) for every input k of j if sensitive(k) extend(k)

Critical Path Tracing Stem Analysis Crithical Path Stem Analysis determine whether stem j is critical by a breadth-first propagation critical(j) frontier = { fanout of j } repeat k = lowest level gate in frontier remove k from frontier if frontier != NULL if propagates(k) add fanouts of k to frontier else critical(j) if propagates(k) and k is critical return TRUE else return FALSE

Critical Path Tracing Directly identifies the fault detected by a test Crithical Path Directly identifies the fault detected by a test Deals with faults only implicitly Based on a path tracing algorithm Approximate method Faster Less memory

PROOFS Only good for synchronous sequential circuits Use iterative array for synchronous sequential circuit X Z D C.L. Y X(1) Y(2) Z(1) Y(1) X(2) Z(2) X(0) Z(0) Y(0) Y(n+1) X(n) Z(n) Y(n)

PROOFS Modified parallel fault simulation Fault-dropping is more effective than parallel fault simulation Parallel fault simulation For (n-1) faults, continue through time frames until all faults are detected or the max time frame is reached F(i): Fault set of faults reaching y(i) but not yet detected Fault Set F(0) X(1) Y(2) Z(1) Y(1) X(2) Z(2) X(0) Z(0) Y(0) Y(n+1) X(n) Z(n) Y(n) Fault Set F(n+1)

PROOFS At the time frame i Perform the fault free simulation For every N faults in F(i) Perform parallel fault simulation Put faults reaching y(i+1) but not reaching z(i) into F(i+1) Y(i+1) X(i) Z(i) Y(i) Fault Set F(i) F(i+1) C.L.

PARIS All primary inputs belong to part A A components with all predecessors in A is also in part A All primary outputs belong to part C A component with all successors in C is also in part C All components not included in either A or C belong to part B

PARIS PARIS Simulate part A Iterate simulation of part B until no more changes occur Simulate part C

PARIS PARIS

PARIS PARIS A reasonable choice for the status words is to simply let them remain unchanged when a new step begins Advantages We spare the overhead to reinitialize all status words at the beginning of each step The number of iterations is often greatly reduced because in general the old status word is a better estimation of the resulting final word than the unknown word Inefficiency Unnecessary multiple evaluations of components during simulation step

Fault Sampling Fault Sampling Reduces the cost of fault simulation by simulating only a random sample of m<M faults Tradeoffs between the cost and accuracy M : number of faults K : number of faults detected by test sequence Fault coverage F=K/M m : number of sample faults k : number of sample faults detected by test sequence Estimated fault coverage f=k/m Determine m such that f belongs to the interval [F-emax, F+emax] with a probability c

Fault Sampling Fault Sampling Probability that T will detect k from m given that it detects K from M Hypergeometric mean and variance For large M, this distribution can be approximated by a normal distribution

Fault Sampling Maximum error To reduce the cost significantly, Then error becomes independent of M Provides an accurate estimate with low cost No information is available about the detection status of faults not included in the sample Difficult to improve fault coverage

Statistical Fault Analysis Fault Sampling STAFAN Low cost alternative to exact fault simulation Processes the results of fault free simulation to estimate its probability of being detected Overall fault coverage is estimated based on the detection probabilities of individual faults Consider T as a set of n independent random vectors Probability that a vector of T detects f is df Probability that n vectors detects f is dnf = 1 - (1-df)n Let F be the set of faults interest Expected number of faults detected by n vectors is Dn = dnf Expected fault coverage is Dn/F

STAFAN Controllability and Observability Fault Sampling Controllability and Observability C1(l) : probability that a vector sets l to value 1 C0(l) : probability that a vector sets l to value 0 B1(l) : probability that a vector propagates a fault effect from l to PO B0(l) : probability that a vector propagates a fault effect from l to PO Estimates after simulating vectors 0-count : number of 0s that occur during fault free simulation 1-count : number of 1s that occur during fault free simulation C0(l) = 0-count / n C1(l) = 1-count / n S(l) = sensitization-count / n When a value is propagated to the gate output

STAFAN Fault Sampling m = AND(i, j, k, l) C1(m) = Prob(i=1, j=1, k=1, l=1) = Prob(i=1, j=1, k=1 | l=1) C1(l) Prob(i=1, j=1, k=1 | l=1) = C1(m)/C1(l) B1(l) = B1(m) Prob(i=1, j=1, k=1 | l=1) = B1(m) C1(m) / C1(l) S(l) = Prob(i=1, j=1, k=1 ) = Prob(i=1, j=1, k=1, l=1 ) + Prob(i=1, j=1, k=1, l=0) = C1(m) + Prob(i=1, j=1, k=1 | l=0)C0(l) Prob(i=1, j=1, k=1 | l=0 ) = ( S(l) - C1(m) ) / CO(l) B0(l) = BO(m) Prob(i=1, j=1, k=1 | l=0) = BO(m) ( S(l) - C1(m) ) / CO(l)

STAFAN OR gate NAND gate NOR gate NOT gate Fault Sampling OR gate B1(l) = B1(m) (S(l) - C0(m))/C1(l) B0(l) = B0(m) C0(m) / C0(l) NAND gate B1(l) = B0(m) C0(m) / C1(l) B0(l) = B1(m) (S(l) - C1(m))/C0(l) NOR gate B1(l) = B0(m) (S(l) - C1(m))/C1(l) B0(l) = B1(m) C1(m) / C0(l) NOT gate B1(l) = B0(m) B0(l) = B1(m)

STAFAN Stem and Reconvergent Fanout Fault Sampling Stem and Reconvergent Fanout Let s be a stem and i, j be fanout branches B1(s)  B1(i) and B1(s)  B1(j) or B1(s)  max[B1(i), B1(j)] If paths through i and j are independent B1(s) = B1(i)  B1(j) = B1(i)+B1(j)-B1(i)B1(j) Upperbound max[B1(i), B1(j)]  B1(s)  B1(i)  B1(j) max[B1(i), B1(j)] depends on circuit topology Let s be a stem and 1, ... , k be fanout branches max [B1(1), ... , B1(k)]  B1(s)  P( ki=1 B1(i)) B1(s) = (1-a) max [B1(1), ... , B1(k)] + a (ki=1 B1(i)) a is an arbitrary constant in the range of [0,1]

STAFAN s stuck at 1 s stuck at 0 Fault Sampling s stuck at 1 D1(l) = Prob( s set to 0 and observed ) = Prob( s set to 0 ) Prob( s is observed | s is 0 ) = B0(s) C0(s) s stuck at 0 D0(s) = B1(s) C1(s) Same computation rules for sequential circuits Results in more approximation Faults are grouped in 3 ranges Faults in a high range is regarded as detected Faults in a low range is regarded as undetected No prediction for faults in a middle range

STAFAN STAFAN requires Fault Sampling STAFAN requires 0-count and 1-count of every gate output and sensitization count of every gate input must be updated in every vector Controllabilities, Observabilities, and detection probabilities are computed after simulating a group of n vectors Since n is large, first operation dominates the complexity

Switch Level Fault Simulation Fault Sampling Complexity Logic values : 0, 1, X, Z Signal strength : Strong, Weak, Charge Wired device Precharge switch

Switch Level Fault Simulation Fault Sampling Precharge f=0 : precharge f=1 : inverter

Switch Level Fault Simulation Fault Sampling Precharge To simulate the precharge switch, the precharge node and its logic values are known Put 0 to the precharge clock and all PIs to X Decide the output to 1

Switch Level Fault Simulation Fault Sampling IN=0 and f=1 Faulty : N2=0 Faulty : N2=Z

Hierarchical Fault Simulation Fault Sampling Use Hardware