Block Diagrams 1

Top-Level Circuit for Lab 4, Tasks 2-4

LAB3 LAB2 A B X Y sel En ‘0’ LFSR CNTR UP = X”3FF” ≠ 0 MISR rst clk en ld LFSR X”00” 8 IVB loadB OR nexti 1 cnz IVA loadA LAB2 A B X Y sel En ‘0’ YSGN nexto XSGN 10 k k9..8 2 k7..0 ≠ 0 = X”3FF” done AND not done step run LAB3

Top-Level Circuit for Lab 4, Tasks 5 & 6

Top-Level Unit for Lab 4, Tasks 5 & 6 entity lab4 is port( CLOCK : in std_logic; BTNL : in std_logic; BTNR : in std_logic; BTNU : in std_logic; BTNS : in std_logic; BTND : in std_logic; SW : in std_logic_vector(7 downto 0); LED : out std_logic_vector(7 downto 0); SEG : out std_logic_vector(6 downto 0); AN : out std_logic_vector(3 downto 0)); ); end entity lab4;

LAB4 for TASK5 LAB3e BTNL BTNL BTNR BTNU BTND BTNS SW CLOCK BTNR LED 8 clk rst BTNL BTNR BTNU BTND BTNS SW next_out BUTTON_UNIT SWITCH_UNIT CLK_RST_1 loadA loadB step run 8 8 clk rst loadA loadB step run IVA IVB clk LAB3e rst XSGN YSGN Xout Yout Aout Bout k clk rst 8 8 8 8 8 8 10 XSGN YSGN X Y A B k hex0 4 hex0 clk hex1 4 SSD_DRIVER hex1 TASK5 hex2 4 hex2 rst LED 4 hex3 hex3 SEG AN 8 7 4 LED SEG AN

LAB3e LAB2 A B sel En X Y ‘0’ LFSR LFSR CNTR UP = X”3FF” ≠ 0 MISR MISR step run loadA IVA loadB IVB 8 loadA loadB 8 OR cnz ld en OR nexti ld en OR nexti LFSR LFSR nexto rst rst clk clk rst rst clk clk AND AND not done X”00” X”00” 8 8 CNTR UP en nexto 1 1 rst rst cnz cnz clk clk 8 8 k 10 A B = X”3FF” 10 k9..8 sel 2 8 done k7..0 LAB2 ≠ 0 En ‘0’ cnz X Y 8 8 en LAB3e nexto en nexto rst rst MISR rst rst MISR clk clk A clk clk B k 8 8 8 8 8 8 10 8 XSGN Xout Aout YSGN Yout Bout kout

BUTTON_UNIT BTNL loadA BTNR loadB BTNU step BTND next_out run BTNS ‘1’ rst rst BTNL Debouncer loadA RED clk clk BTNR Debouncer RED loadB rst clk rst rst BTNU Debouncer step RED clk clk rst rst BTND Debouncer next_out RED clk clk rst rst clk rst ‘1’ run D Q BTNS Debouncer en RED clk clk

SWITCH_UNIT 8 8 SW IVA 8 IVB

CLK_RST_1 CLOCK clk BTNL rst BTNR

SSD_DRIVER SEG(6..0) Counter UP q(k-1..k-2) Counter UP Counter UP clk AN OC Counter UP rst OC – One’s Complement

LAB4 for TASK6 LAB3e BTNL BTNL BTNR BTNU BTND BTNS SW CLOCK BTNR LED 8 clk rst BTNL BTNR BTNU BTND BTNS SW next_out BUTTON_UNIT SWITCH_UNIT CLK_RST_2 loadA loadB step run 8 8 clk rst loadA loadB step run IVA IVB clk LAB3e rst XSGN YSGN Xout Yout Aout Bout k clk rst 8 8 8 8 8 8 10 XSGN YSGN X Y A B k hex0 4 hex0 clk hex1 4 SSD_DRIVER hex1 TASK5 hex2 4 hex2 rst LED 4 hex3 hex3 SEG AN 8 7 4 LED SEG AN

CLK_RST_2 clkfx_obufg clkFX DCM_SP BUFG clk clk_ibufg clk0_obufg IBUFG ‘0’ clkfx_obufg clkFX DCM_SP BUFG clkfx clk clk_ibufg clk0_obufg IBUFG clk100 CLOCK clkin clk0 BUFG 1 BUFGMUX BTNL rst_or rst BTNR rst clkfb locked

User Constraint File (UCF) 14

User Constraint File (UCF) - LEDs NET "LED<0>" LOC = "U16" | IOSTANDARD = "LVCMOS33"; NET "LED<1>" LOC = "V16" | IOSTANDARD = "LVCMOS33"; NET "LED<2>" LOC = "U15" | IOSTANDARD = "LVCMOS33"; NET "LED<3>" LOC = "V15" | IOSTANDARD = "LVCMOS33"; NET "LED<4>" LOC = "M11" | IOSTANDARD = "LVCMOS33"; NET "LED<5>" LOC = "N11" | IOSTANDARD = "LVCMOS33"; NET "LED<6>" LOC = "R11" | IOSTANDARD = "LVCMOS33"; NET "LED<7>" LOC = "T11" | IOSTANDARD = "LVCMOS33";

User Constraint File (UCF) - SSD # Seven Segment Displays NET "SEG<0>" LOC = "T17" | IOSTANDARD = "LVCMOS33"; NET "SEG<1>" LOC = "T18" | IOSTANDARD = "LVCMOS33"; NET "SEG<2>" LOC = "U17" | IOSTANDARD = "LVCMOS33"; NET "SEG<3>" LOC = "U18" | IOSTANDARD = "LVCMOS33"; NET "SEG<4>" LOC = "M14" | IOSTANDARD = "LVCMOS33"; NET "SEG<5>" LOC = "N14" | IOSTANDARD = "LVCMOS33"; NET "SEG<6>" LOC = "L14" | IOSTANDARD = "LVCMOS33"; NET "AN<0>" LOC = "N16" | IOSTANDARD = "LVCMOS33"; NET "AN<1>" LOC = "N15" | IOSTANDARD = "LVCMOS33"; NET "AN<2>" LOC = "P18" | IOSTANDARD = "LVCMOS33"; NET "AN<3>" LOC = "P17" | IOSTANDARD = "LVCMOS33";

User Constraint File (UCF) Switches NET "SW<0>" LOC = "T10" | IOSTANDARD = "LVCMOS33"; NET "SW<1>" LOC = "T9" | IOSTANDARD = "LVCMOS33"; NET "SW<2>" LOC = "V9" | IOSTANDARD = "LVCMOS33"; NET "SW<3>" LOC = "M8" | IOSTANDARD = "LVCMOS33"; NET "SW<4>" LOC = "N8" | IOSTANDARD = "LVCMOS33"; NET "SW<5>" LOC = "U8" | IOSTANDARD = "LVCMOS33"; NET "SW<6>" LOC = "V8" | IOSTANDARD = "LVCMOS33"; NET "SW<7>" LOC = "T5" | IOSTANDARD = "LVCMOS33";

User Constraint File (UCF) Buttons NET "BTNS" LOC = "B8" | IOSTANDARD = "LVCMOS33"; BTNS NET "BTNU" LOC = "A8" | IOSTANDARD = "LVCMOS33"; BTNU NET "BTNL" LOC = "C4" | IOSTANDARD = "LVCMOS33"; BTNL NET "BTND" LOC = "C9" | IOSTANDARD = "LVCMOS33"; BTND NET "BTNR" LOC = "D9" | IOSTANDARD = "LVCMOS33"; BTNR

User Constraint File (UCF) CLOCK # Buttons NET "CLOCK" LOC = "V10" | IOSTANDARD = "LVCMOS33";

Seven Segment Displays 21

4-Digit Seven Segment Display

Patterns for Decimal Digits

Patterns for Hexadecimal Digits

Connection to FPGA Pins

Multiplexing Digits

Time-Multiplexed Seven Segment Display

SSD_DRIVER SEG(6..0) Counter UP q(k-1..k-2) Counter UP Counter UP clk AN OC Counter UP rst OC – One’s Complement

Size of the counter 2k * TCLK ≈ 16 ms fCLK = 100 MHz k = ?

Digital Clock Managers Variable Clock Frequency and Variable Clock Frequency 30

Clock Management Clock sources are generated off of the FPGA Clock source needs to enter the FPGA Clock needs to be “de-jittered” Clock naturally has non-constant duty cycle and period Clock needs to reach the rest of the chip

Clock Management Ideal clock has one frequency Clock jitter is the undesired deviation in the timing of clock edges We can see the jitter in the top (yellow) trace Blue clock is de-jittered

Clock Management CLOCK Enters FPGA and enters IBUFG ‘0’ clkfx_obufg clkFX DCM_SP BUFG clkfx clk clk_ibufg clk0_obufg IBUFG clk100 CLOCK clkin clk0 BUFG 1 BUFGMUX BTNL rst_or rst BTNR rst clkfb locked CLOCK Enters FPGA and enters IBUFG Output of BUFGMUX goes to the rest of the FPGA Invert of LOCKED signal is used as a reset for the top-level circuit To simulate, include the following lines in the library section library UNISIM; use UNISIM.vcomponents.all;

Digital Clock Manager DCM can also change clock frequency CLK2X doubles frequency CLKDV and CLKFX change the frequency based on the generics (see instantiation)

Digital Clock Manager

Digital Clock Manager

DCM_SP Instantiation (1) DCM_SP_inst : DCM_SP generic map ( CLKDV_DIVIDE => 2.0, -- CLKDV divide value -- (1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,7,7.5,8,9,10,11,12,13,14,15,16). -- Divide value on CLKFX outputs - D - (1-32) -- Multiply value on CLKFX outputs - M - (2-32) -- CLKIN divide by two (TRUE/FALSE) -- Input clock period specified in nS -- Output phase shift (NONE, FIXED, VARIABLE) -- Feedback source (NONE, 1X, 2X) CLKFX_DIVIDE => …………., CLKFX_MULTIPLY => ………, CLKIN_DIVIDE_BY_2 => FALSE, CLKIN_PERIOD => 10.0, CLKOUT_PHASE_SHIFT => "NONE", CLK_FEEDBACK => "1X”,

DCM_SP Instantiation (2) -- SYSTEM_SYNCHRNOUS or SOURCE_SYNCHRONOUS DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- Unsupported generics - Do not change value DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW", DSS_MODE => "NONE", DUTY_CYCLE_CORRECTION => TRUE, FACTORY_JF => X"c080", PHASE_SHIFT => 0, STARTUP_WAIT => FALSE -- Amount of fixed phase shift (-255 to 255) -- Delay config DONE until DCM_SP LOCKED (TRUE/FALSE) )

DCM_SP Instantiation (3) port map ( CLK0 => …………., -- 0 degree clock output CLK180 => open, -- 180 degree clock output CLK270 => open, -- 270 degree clock output CLK2X => open, -- 2X clock frequency clock output CLK2X180 => open, -- 2X clock frequency 180 degree clock output CLK90 => open, -- 90 degree clock output CLKDV => open, -- Divided clock output CLKFX => …………, -- Digital Frequency Synthesizer (DFS) output CLKFX180 => open, -- 180 degree CLKFX output LOCKED => …………, -- DCM_SP Lock Output

DCM_SP Instantiation (4) PSDONE => open, -- Phase shift done output STATUS => open, -- DCM_SP status output CLKFB => …………., -- Clock feedback input CLKIN => ………….., -- Clock input DSSEN => ‘0’, -- Unsupported, specify to GND PSCLK => clk_ibufg, -- Phase shift clock input PSEN => ‘0’, -- Phase shift enable PSINCDEC => ‘0’ , -- Phase shift increment/decrement input RST => ………… -- Active high reset input );

Library and Package In order to compile, simulate and synthesize a circuit including DCM_SP, you need to include in the top-level circuit: library UNISIM; use UNISIM.vcomponents.all;

Clock Buffers BUFG_inst : BUFG port map ( O => O, I => I); Dedicated clock route for reaching the rest of the chip at the same time Should be used for all generated clocks Output from DCM Output from clock divider circuits IBUFG_inst : IBUFG generic map ( IOSTANDARD => "DEFAULT") port map ( O => O, I => I); Dedicated clock route for reaching a DCM and the rest of the chip Should be used for a clock port

Clock Multiplexer BUFGMUX_inst : BUFGMUX generic map ( CLK_SEL_TYPE => "SYNC" -- Glitchles ("SYNC") or fast ("ASYNC") clock switch-over ) port map ( O => …….., -- 1-bit output: Clock buffer output I0 => …….., -- 1-bit input: Clock buffer input (S=0) I1 => …….., -- 1-bit input: Clock buffer input (S=1) S => ……… -- 1-bit input: Clock buffer select );