101-1 Under-Graduate Project Techniques in VLSI design Speaker: Yu-Min Lin Advisor: Prof. An-Yeu Wu Date: 2012/10/23 Some slides come from Prof. Chien’s course — DSP in VLSI Design

Outline Techniques in VLSI design Iteration Bound Pipelining & Parallel Retiming Unfolding / Folding

Critical Path The path with the longest computation time among all paths that contain zero delays

Loop Bound Loop — A directed path that begins and ends at the same node Loop Bound — The lower bound on the loop computation time Loop Bound T = t / w t — loop computation time w — # of delays in the loop

Iteration Bound Critical Loop — Iteration Bound — The loop with the maximum loop bound Iteration Bound — Loop bound of the critical loop

Iteration Bound Iteration bound is the lower bound on the sample/clock period of the DSP program regardless of the amount of computing resources available

Pipelining & Parallel Pipelining and parallel are the most important design techniques in VLSI DSP systems Pipelining — Different function units working in parallel Parallel — Duplicated function units working in parallel

Pipelining & Parallel

Pipelining How to do pipelining? Drawbacks of Pipelining — Put pipelining registers across an feed-forward cutset Drawbacks of Pipelining — Increasing latency Increasing the number of registers

Parallel

Parallel Drawbacks of Pipelining — Large hardware cost

Retiming Retiming — Applications of retiming — A transformation technique used to change the locations of delay elements in circuit without affecting the input/output characteristics Applications of retiming — Reducing the clock period Reducing the number of registers

Retiming Pipelining is a special case of retiming

Retiming Reducing the clock period —

Retiming Reducing the number of registers —

Unfolding Unfolding is similar to parallel processing

Unfolding Sample/Clock period reduction —

Folding