Basic electrical properties

MOS TRANSISTOR FIGURE OF MERIT Electron mobility (100) oriented n-type is larger than (111) oriented surface, it is about 3times larger than p type(111) oriented hole mobility. Surface mobility is depend on Vgs-Vt For faster nMos – choose 100 oriented ptype substrate. Bulk mobility μn = 1250cm2/v.sec μp= 480 cm2/v.sec

PASS TRANSISTOR isolated nature of gate allows MOS transistor to used as switches in series with line carrying logic level Application Pass transistor and switching logic array (AND array)

nMOS inverter An inverter circuit producing a complete range of logic circuits. A simple inverter circuit - transistor with source is gnd & RL from the drain to the VDD· The output from drain and the input applied b/w gate and gnd . But, resistors are not conveniently produced on the silicon substrate occupy large areas .- use depletion mode tr. as load.

Cont.. Features of the n-MOS inverter Ids is same for both tr with no current drawn from o/p Dep mode tr is ON Vgs =0 Dep – pull-up(p.u) & enh – pull down (p.d)

Cont… During transition, the slope of transfer characteristics det. The gain Gain = Vout/ Vin

ALTERNATIVE FORMS OF PULL –UP 1.Load resistance RL : This arrangement consists of a load resistor as a pull-up Not widely used because of the large space requirements

CONT… 2. nMOS depletion mode transistor pull-up : it consists of a depletion mode transistor as p.u Dissipation is high , since rail to rail current flows when Vin = logical 1

Cont… 3.nMOS enhancement mode pull-up Dissipation is high since current flows when Vin =logical 1 Vout can never reach VDD (logical I) if VGG = VDD VGG may be derived from a switching source

Cont.. 4.Complementary transistor pull-up (CMOS) No current flows either for logical 0 or for logical 1 inputs. Full logical 1 and 0 levels are presented at the output. For devices of similar dimensions the p-channel is slower than the n-channel device.

Vin = VDD + Vtp +Vtn (βn + βp)1/2 / 1+ (βn + βp)1/2 Since both transistors are in saturation, they act as current sources. If βn= βp and Vtn= - Vtp Vin = 0.5 Vdd = Vout Since only at this point will the two β factors be equal. But for βn= βp the device geometries must be such that µpWp/Lp = µn Wn/Ln Wp/Lp = 2.5 Wn/Ln The mobility µ is affected by the transverse electric field.   µ= µz (1 – φ (Vgs – Vt))-1 µz - mobility with zero transverse field. φ - constant approximately equal to 0.05

Bicmos inverter Output logic levels will be good & will be close to rail voltages since VCEsat  is quite small & VBE= 0.7V. inverter has high noise margins  Inverter has high input impedance & low output impedance  Inverter has high drive capability but occupies a relatively small area  However, this is not a good arrangement to implement since no discharge path exists for current from the base of either bipolar transistor when it is being turned   off

Improved BiCMOS inverter using MOS transistor or base current discharge