CDM Circuit Analysis with VFTLP Accurate VFTLP Measurements Provide Accurate CDM Design Data Barth 2018 Showcase

CDM Protection Circuit Typically uses a small diode Minimum capacitance Small size for minimum time delay Gate xxx diodes have minimal delay It must clamp the ESD threat rapidly Use 0.6 to 1.0 ns IEC Spec The CDM protection circuit is typically a small diode with low capacitance to not affect high speed circuits. The goal is to keep its dimensions small for minimum time delay, but large enough to not be damaged by the specified ESD threat. It must clamp the ESD threat rapidly Gate coupled diodes have the least delay, and produce minimal IVI Threat. Barth 2018 Showcase

The IVI (transient) in VFTLP We developed this analysis to demonstrate how the Initial Voltage Impulse is created as a triangular waveform. This illustrates the blue ESD threat voltage rising in 100 ps. The current is delayed by 20 ps before it completes its circuit and conducts to clamp the ESD threat voltage. Each voltage increase begins another group of carriers on their way through the semiconductor with their own 20 ps time delay. The resulting triangular voltage in black at the bottom of the plot is the resulting IVI or “transient” gate threat voltage as it is also called. We can discuss this and other options of our VFTLP system at our booth #200 in the exhibit hall. Barth 2018 Showcase

VFTLP Voltage Waveforms This is the voltage waveform across a CDM protection circuit using a 2 ns wide test pulse. The initial Voltage Impulse ( IVI) is caused by the delay time through the semiconductor clamp. Barth 2018 Showcase

VFTLP Average & Peak Voltage This is the Barth I-V plot which adds the peak voltage gate threat. It shows the average voltage vs. current, along with the peak voltage plotted together because they are both created at the same current. Barth 2018 Showcase

Peak Voltage Decrease Barth 2018 Showcase This shows the maximum peak voltage in black While the average voltage after the peak voltage is increasing, when succeeding peak voltages begin to decrease, it indicates that the CDM protection circuit damage has begun. If circuit failure is net indicated by a major increase in leakage current, any decrease the peak voltage waveform amplitude indicates protection circuit damage. Although the average voltage is increasing their differences can be difficult to see because they do not have much amplitude increase for each increase in test pulse amplitude. Some CDM test circuits have leakage changes during the test that make it difficult to identify its failure. Decreases in peak voltage are a definite indicator of circuit failure. Barth 2018 Showcase

IVI Abrupt Decrease Barth 2018 Showcase Our I-V plot in red, includes the Peak Voltage data, shown in blue. This DUT had a few leakage transitions, that are shown in green; However the increased leakage that corresponded with the abrupt decrease in the IVI amplitude (blue) at about 4.5 amps are both definite indicators of CDM circuit failure. The circuit failure is not always an abrupt increase in current. The other leakage transitions shown here have unknown causes. Barth 2018 Showcase

Complex Leakage Transitions The many leakage current transitions in green, make it difficult to identify the basic CDM protection circuit failure current level. Again, the abrupt decrease in the IVI amplitude, in blue, clearly indentifies CDM protection circuit failure. Our 4012 VFTLP system has an option to add 0.6 to 1.0 ns risetimes to the standard 0.1, 0.2 and 0.4 ns test pulse risetime specs. This meets the IEC Spec for the ESDA 5.6 HMM test spec. (although this group has not yet decided to add dV/dt specs to device testing. Barth 2018 Showcase

For More VFTLP & CDM Testing Information Visit our Booth #200 Saved at: 1Data\ESD\ESDA\Shawcase\2018\CDM Circuit Analysis with VFTLP Barth 2018 Showcase