45nm example2 library Validation With Crossfire™ Fractal Technologies 45nm example2 library Validation With Crossfire™ 12/1/2018 Fractal Technologies Confidential

Quality in Design Formats Formats checked Formats of example2 library checked: Spice Lpe_worst spice Verilog 2 files, 10 flavors With/without pwr pins, TETRAMAX, NTC, RECREM VHDL: Component Entities Liberty NLDM : 19 full databases CCS : 14 full databases (ff, sf, fs, ss, and tt missing) ECSM: 19 full databases LEF: 9 technology variants Every LEF has full technology PLIB: 9 technology variants GDSII Cadence CDB: layout, schematic, symbol views Milky Way CEL+FRAM FRAM-only (FRAM supplied twice) Colors used in this report: Black lines describe checks Green refers to checks passed successfully Red indicates checks that failed, potential library errors Additional formats supported Documentation (html or pdf) OpenAccess Other ASCII based formats SLIB FastScan, atpg Logicvision 12/1/2018 Quality in Design Formats

Quality in Design Formats Cell-presence Created cell lists used for presence checks: Schematics: 812 cells (Cells with a function, incl. TAPCELL) EXTRA: 15 cells (Functional cells, separately provided) FILLS: 13 cells (Filler cells) DCAPS: 20 cells (Decoupling cells) ISO: 8 cells LH Level Shifters: 8 cells HL Level Shifters: 4 cells Remarks: Technology defined in both std and EXTRA LEF file Milky Way FRAM views provided twice CCS misses 5 characterization corners (ff, sf, tt, ss and fs) present in NLDM and ECSM ECSM corners in different locations (timing_power_noise and signal_storm) 12/1/2018 Quality in Design Formats

Cell Presence Layout Databases Schematics Extra Dcaps Fills LH-lvl-shift HL-lvl-shift Iso-cells lef-xlm (9 databases) 812/812 15/15 20/20 13/13 8/8 4/4 plib-xlm (9 databases) 0/15 mw-CEL-cell_frame mw-FRAM-cell_frame mw-FRAM-frame_only gdsii cdb-layout 488/812 17/20 0/8 0/4 cdb-schematic 487/812 5/13 cdb-symbol 0/13 CDB details, file transfer problem? Dcap cells missing: CAP16B DCAP32B DCAP64B Schematic: has only GFILL cells, no FILL* -> GFILL cells have no symbol! All views: cells from AN2 to LNSN, all cells from LNSN to OR4 are missing Layout: has LNSN cell but does not exist anywhere else 12/1/2018 Quality in Design Formats

Cell Presence Netlist and Behavior Schematics Extra Dcaps Fills LH-lvl-shift HL-lvl-shift Iso-cells Lpe_worst 93/812 0/15 0/20 0/13 0/8 0/4 spice 812/812 20/20 5/13 8/8 4/4 verilog 811/812 15/15 verilog-pwr tetramax All other Verilog flavours (10) VHDL component + entity Details: lpe-worst: file transfer problem? No .ends last subcircuit spice: only GFILL cells, no FILL cells Verilog, VHDL: no tapcell 12/1/2018 Quality in Design Formats

Quality in Design Formats Cell Presence NLDM Schematics Extra Dcaps Fills LH-lvl-shift HL-lvl-shift Iso-cells nldm-bc 812/812 15/15 20/20 0/13 8/8 4/4 nldm-bc99 nldm-bc1.21-99 0/812 0/15 0/20 0/8 nldm-bc0.99-121 0/4 Lt, ml, tc, wc, wcl, wcz nldm-tt nldm-sf nldm-ss nldm-fs nldm-ff Structure of NDLM characterization corners bc bc 1.21-1.21 bc-EXTRA bc 1.21-0.99 bc 0.99 bc 0.99-0.99 bc-0.99 EXTRA bc 0.99 -1.21 12/1/2018 Quality in Design Formats

Cell Presence CCS & ECSM CCS corners identical to NLDM: -lt*, -ml*, -tc*, -wc*, -wcl*, -wcz* Missing CCS corners: tt, sf, fs, ss, and ff ECSM corners identical to NLDM: -lt*, -ml*, -tc*, -wc*, -wcl*, -wcz*, -tt*, -sf*, -fs*, -ss*, -ff* ECSM files are not in one place: Tt, sf, ss, fs and ff corners inside timing_power_noise All other ecsm files in signal_storm 12/1/2018 Quality in Design Formats

Hierarchy consistency All databases contain master cells for all instances: Cadence CDB, Milky Way, gdsII, spice, verilog, VHDL Exceptions: CDB schematic: ipin, opin, iopin, nch, pch, ndio symbol views missing 12/1/2018 Quality in Design Formats

Quality in Design Formats Terminals & Pins (1) Are the same pins defined in all formats? Golden Reference used: verilog Check passed all formats (except gdsII) CDB layout view has BIDIRECTIONAL pins instead of input/output Example lib 2 Crossfire error visualization 12/1/2018 Quality in Design Formats

Quality in Design Formats Terminals & Pins (2) Most pins are drawn in M1 Applies to CDB, Milky Way, LEF, PLIB Exceptions having pins in M2: NR2, DFCNQD1, AI21, D3D2, ND2D4, D2D3, D2D2, MUX2ND, MUX2ND, MUX2D1, DFQD1, DFCNQD Extra VDDL pin for LH level shifters No VDDH pin for HL level shifters? Antenna symbol/schematic has no VDD pin All other symbol views have additional VDD/VSS pins Labels present in M1TXT or M2TXT Applies to CDB, MilkyWay CEL, and gdsII 12/1/2018 Quality in Design Formats

Quality in Design Formats Layout vs. layout Checks identity between polygons: layout-vs-layout or abstract-vs-layout Performs Boolean mask XOR operations Detailed check example: Abstract vs Layout “11 0” in GDSII <= “M1” LEF GDSII M1, M2, VIA equals LEF PLIB MilkyWay cell-frame FRAM MilkyWay frame-only FRAM GDSII all layers equals: CDB-layout MilkyWay cell-frame CEL Interview showing PLIB, LEF, GDSII, CDB and MilkyWay 12/1/2018 Quality in Design Formats

Quality in Design Formats Abutment All cells checked for self-symmetry and left/right abutment (alignment on cell-boundary) with reference cell (INVD): Check passed GDSII, all layers Example: Poly abutment error on multi-pitch level-shifter LH cells Only, poly not e.g. nwell 12/1/2018 Quality in Design Formats

Quality in Design Formats Routability (1) Checks if signal-pins can be routed to cell-boundary Uses fast internal maze router Users select layers (e.g. M1 only) or special rules (e.g. double-via’s on outputs of high-drive cells) Technology settings (rules, vias, pitch) read from LEF technology Results All cells are compatible for height and pitch Total checked 3951 pins, 880 cells 2666 routable in M1, 67% above average (55%) 12/1/2018 Quality in Design Formats

Quality in Design Formats Routability (2) Only 1 pin is only routable only in M3: Cell DFCNQD1, pin D 12/1/2018 Quality in Design Formats

Functional Equivalence Verified functional equivalence between Verilog, SPICE, VHDL and Liberty Checks equivalence of Boolean expressions from different databases For (schematics) & SPICE, expressions are automatically extracted. Spice vs nldm: ok Verilog vs nldm: ok Tetramax vs Verilog: ok Crossfire feedback showing equations extracted from SPICE 12/1/2018 Quality in Design Formats

Quality in Design Formats Characterization Cross-checks arc-presence between Liberty, VHDL and Verilog Sanity checks on characterized delay and power numbers All NLDM delays increase with increasing output capacitance SDF expressions equal Liberty when expressions Arc conditions are consistent (no redundant or conflicting conditions) 12/1/2018 Quality in Design Formats

CCS Characterization (1) Many cells do not have a single peak current (tc corner) Current curves generally have a “correction current” at the tail (tc corner) Cell AN2, output_current_fall A2->Z Cell DFCND, output_current_rise CP->Q 12/1/2018 Quality in Design Formats

CCS Characterization (2) 86 Cells exhibit peak-current anomalies (tc corner) E.g. Cell AN3, rise current A3Z Curve for slew 0.02, cap=0.1739 has 50 samples instead of 10 Cell AN2, CCS peak currents Cell AN2, CCS current curve 12/1/2018 Quality in Design Formats

CCS Characterization (3) More examples of CCS peak current anomalies (tc corner) Cell NR4, CCS output_current_rise A4 -> ZN Cell MUX2, CCS output_current_rise S -> ZN 12/1/2018 Quality in Design Formats

CCS Characterization (4) Tristate buffer cells use different capacitance values for CCS and NLDM, e.g. : tc corner, cell BUFTD, cell_rise: I  Z CCS indices: [0.00164, 0.008240, 0.021430, 0.047820, 0.10060, 0.20610, 0.41720] NLDM indices: [0.0065720, 0.013170, 0.026360, 0.052750, 0.1055, 0.21110, 0.42220] CCS delays for tc corner are identical to NLDM delays 2%/0.01 tolerance values 12/1/2018 Quality in Design Formats

ECSM Characterization Many ECSM-curves have large deviations (20-300%) between ECSM and NLDM delay values, e.g.: TC corner, cell AOI22D1, cell_fall: A1  ZN, index (1,1) (cap=0.00045pf, slew=0.004) 33% deviation of delay value (0.01285 vs 0.0169) Cell AOI22, CCS-NLDM deviation Cell AOI22, clip from ECSM tc corner 12/1/2018 Quality in Design Formats Cell AN2, no CCS-NLDM deviation, typical

Characterization Comparison Histogram plot of cell-rise delays bc, tc and wc corners Delay cells excluded 12/1/2018 Quality in Design Formats

Quality in Design Formats Conclusions Summary of inconsistencies detected: Structure Technology defined in both std and EXTRA LEF file Milky Way FRAM views provided twice CCS misses 5 characterization corners (ff, sf, tt, ss and fs) ECSM corners in different locations Presence Missing EXTRA cells in MilkyWay, PLIB, spice Level shifters missing from tt, sf, fs, ss, and ff Incomplete CDB and lpe databases Characterization CCS peak current anomalies in 86 cells CCS capacitance values different for BUFT cells ECSM vs NLDM mismatches 12/1/2018 Quality in Design Formats