CS61C : Machine Structures Lecture 5. 1 CS61C : Machine Structures Lecture 5.1.1 CPU Design I 2004-07-19 Kurt Meinz inst.eecs.berkeley.edu/~cs61c Greet class

Review: Verilog Dataflow Paradigm module and_or(Z, A, B, Sel); input A, B, Sel output Z; wire Z; assign #5 Z = Sel ? (A & B) : (A | B); endmodule Continuous Assignment: Limited to simple operations Simple translation to structural Trinary if ( ? : ), logic operators Excellent for CL.

Review: What’s a reg?? Output types: Why? Structural  Wire wire a,b,c; and (a, b, c); Continuous Assign  Wire wire a,b,c; assign a = b & c; Procedural Assign  REG wire b,c; reg a; always @ (b or c) a = b & c; Why? Structural, continuous always function of current input.  simple wire REG  Verilog has to remember value

Anatomy: 5 components of any Computer Personal Computer This week Keyboard, Mouse Computer Processor Memory (where programs, data live when running) Devices Disk (where programs, data live when not running) Control (“brain”) Input That is, any computer, no matter how primitive or advance, can be divided into five parts: 1. The input devices bring the data from the outside world into the computer. 2. These data are kept in the computer’s memory until ... 3. The datapath request and process them. 4. The operation of the datapath is controlled by the computer’s controller. All the work done by the computer will NOT do us any good unless we can get the data back to the outside world. 5. Getting the data back to the outside world is the job of the output devices. The most COMMON way to connect these 5 components together is to use a network of busses. Datapath (“brawn”) Output Display, Printer

Design a processor: step-by-step Requirements of the Instruction Set Outline Design a processor: step-by-step Requirements of the Instruction Set Hardware components that match the instruction set requirements Here is an outline of today’’s lecture. Mainly, we will be building a datapath step by step for a subset of the MIPS instruction set. +1 = 4 min. (X:44)

How to Design a Processor: step-by-step 1. Analyze instruction set architecture (ISA) => datapath requirements meaning of each instruction is given by the register transfers datapath must include storage element for ISA registers datapath must support each register transfer 2. Select set of datapath components and establish clocking methodology 3. Assemble datapath meeting requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic

Step 1: The MIPS Instruction Formats All MIPS instructions are 32 bits long. 3 formats: R-type I-type J-type The different fields are: op: operation (“opcode”) of the instruction rs, rt, rd: the source and destination register specifiers shamt: shift amount funct: selects the variant of the operation in the “op” field address / immediate: address offset or immediate value target address: target address of jump instruction op rs rt rd shamt funct 6 11 16 21 26 31 6 bits 5 bits op rs rt address/immediate 16 21 26 31 6 bits 16 bits 5 bits op target address 26 31 6 bits 26 bits One of the most important thing you need to know before you start designing a processor is how the instructions look like. Or in more technical term, you need to know the instruction format. One good thing about the MIPS instruction set is that it is very simple. First of all, all MIPS instructions are 32 bits long and there are only three instruction formats: (a) R-type, (b) I-type, and (c) J-type. The different fields of the R-type instructions are: (a) OP specifies the operation of the instruction. (b) Rs, Rt, and Rd are the source and destination register specifiers. (c) Shamt specifies the amount you need to shift for the shift instructions. (d) Funct selects the variant of the operation specified in the “op” field. For the I-type instruction, bits 0 to 15 are used as an immediate field. I will show you how this immediate field is used differently by different instructions. Finally for the J-type instruction, bits 0 to 25 become the target address of the jump. +3 = 10 min. (X:50)

Step 1: The MIPS-lite Subset for today ADD and SUB addU rd,rs,rt subU rd,rs,rt OR Immediate: ori rt,rs,imm16 LOAD and STORE Word lw rt,rs,imm16 sw rt,rs,imm16 BRANCH: beq rs,rt,imm16 op rs rt rd shamt funct 6 11 16 21 26 31 6 bits 5 bits op rs rt immediate 16 21 26 31 6 bits 16 bits 5 bits op rs rt immediate 16 21 26 31 6 bits 16 bits 5 bits In today’s lecture, I will show you how to implement the following subset of MIPS instructions: add, subtract, or immediate, load, store, branch, and the jump instruction. The Add and Subtract instructions use the R format. The Op together with the Func fields together specified all the different kinds of add and subtract instructions. Rs and Rt specifies the source registers. And the Rd field specifies the destination register. The Or immediate instruction uses the I format. It only uses one source register, Rs. The other operand comes from the immediate field. The Rt field is used to specified the destination register. (Note that dest is the Rt field!) Both the load and store instructions use the I format and both add the Rs and the immediate filed together to from the memory address. The difference is that the load instruction will load the data from memory into Rt while the store instruction will store the data in Rt into the memory. The branch on equal instruction also uses the I format. Here Rs and Rt are used to specified the registers we need to compare. If these two registers are equal, we will branch to a location offset by the immediate field. Finally, the jump instruction uses the J format and always causes the program to jump to a memory location specified in the address field. I know I went over this rather quickly and you may have missed something. But don’t worry, this is just an overview. You will keep seeing these (point to the format) all day today. +3 = 13 min. (X:53) op rs rt immediate 16 21 26 31 6 bits 16 bits 5 bits

Step 1: Register Transfer Language RTL gives the meaning of the instructions All start by fetching the instruction {op , rs , rt , rd , shamt , funct} = MEM[ PC ] {op , rs , rt , Imm16} = MEM[ PC ] inst Register Transfers ADDU R[rd] = R[rs] + R[rt]; PC = PC + 4 SUBU R[rd] = R[rs] – R[rt]; PC = PC + 4 ORI R[rt] = R[rs] | zero_ext(Imm16); PC = PC + 4 LOAD R[rt] = MEM[ R[rs] + sign_ext(Imm16)];PC = PC + 4 STORE MEM[ R[rs] + sign_ext(Imm16) ] = R[rt];PC = PC + 4 BEQ if ( R[rs] == R[rt] ) then PC = PC + 4 + sign_ext(Imm16)] << 2 else PC = PC + 4

Step 1: Requirements of the Instruction Set Memory (MEM) instructions & data Registers (R: 32 x 32) read RS read RT Write RT or RD PC Extender (sign extend) Add and Sub register or extended immediate Add 4 or extended immediate to PC

Step 1: Abstract Implementation Control Ideal Instruction Memory Control Signals Instruction Conditions Rd Rs Rt 5 5 5 Instruction Address A Data Address Data Out Clk PC Rw Ra Rb ALU 32 32 32 Ideal Data Memory Next Address 32 32-bit Registers Data In B One thing you may noticed from our last slide is that almost all instructions, except Jump, require reading some registers, do some computation, and then do something else. Therefore our datapath will look something like this. For example, if we have an add instruction (points to the output of Instruction Memory), we will read the registers from the register file (Ra, Rb and then busA and busB). Add the two numbers together (ALU) and then write the result back to the register file. On the other hand, if we have a load instruction, we will first use the ALU to calculate the memory address. Once the address is ready, we will use it to access the Data Memory. And once the data is available on Data Memory’s output bus, we will write the data to the register file. Well, this is simple enough. But if it is this simple, you probably won’t need to take this class. So in today’s lecture, I will show you how to turn this abstract datapath into a real datapath by making it slightly (JUST slightly) more complicated so it can do real work for you. But before we do that, let’s do a quick review of the clocking methodology +3 = 16 (X:56) Clk Clk 32 Datapath

How to Design a Processor: step-by-step 1. Analyze instruction set architecture (ISA) => datapath requirements meaning of each instruction is given by the register transfers datapath must include storage element for ISA registers datapath must support each register transfer 2. Select set of datapath components and establish clocking methodology 3. Assemble datapath meeting requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic (hard part!)

Step 2a: Components of the Datapath Combinational Elements Storage Elements Clocking methodology

Combinational Logic: 16-bit Sign Extender //Sign extender from 16- to 32-bits. module signExtend (in,out); input [15:0] in; output [31:0] out; reg [31:0] out; assign out = { in[15], in[15], in[15], in[15], in[15], in[15], in[15], in[15], in[15:0] }; endmodule // signExtend

Combinational Logic: 2-bit Left Shift // 32-bit Shift left by 2 module leftShift2 (in,out); input [31:0] in; output [31:0] out; assign out = { in[29:0], 1'b0, 1'b0 }; endmodule // leftShift2 (Also: assign out = in[29:0] << 2;)

Combinational Logic: More Elements CarryIn Adder MUX ALU A 32 Sum Adder 32 B Carry 32 Select A 32 MUX Y 32 B 32 Based on the Register Transfer Language examples we have so far, we know we will need the following combinational logic elements. We will need an adder to update the program counter. A MUX to select the results. And finally, an ALU to do various arithmetic and logic operation. +1 = 30 min. (Y:10) OP A 32 ALU Result 32 B 32

Combinational Logic: 32-bit Adder //Behavioral model of 32-bit adder. module add32 (S,A,B); input [31:0] A,B; output [31:0] S; reg [31:0] S; always @ (A or B) S = A + B; endmodule // add32 // 32 bits How do we make this dataflow?

Combinational Logic: 32-bit Mux // Behavioral model of 32-bit wide // 2-to-1 multiplexor. module mux32 (in0,in1,select,out); input [31:0] in0,in1; input select; output [31:0] out; reg [31:0] out; always @ (in0 or in1 or select) if (select) out=in1; else out=in0; endmodule // mux32

CL: ALU for MIPS-lite (1/4) Addition, subtraction, logical OR, ==: ADDU R[rd] = R[rs] + R[rt]; ... SUBU R[rd] = R[rs] – R[rt]; ... ORI R[rt] = R[rs] | zero_ext(Imm16)... BEQ if ( R[rs] == R[rt] )... Test to see if output == 0 for any ALU operation gives == test. How? P&H Section 4.5 also adds AND, Set Less Than (1 if A < B, 0 otherwise) Behavioral ALU follows sec 4.5

CL: ALU (2/4) //Behavioral model of ALU: // 8 functions and "zero" flag, // A is top input, B is bottom, // according to P&H figure 5.19. module ALU (A,B,control,zero,result); input [31:0] A, B; input [2:0] control; output zero; // used for beq,bne output [31:0] result; reg [31:0] result, temp; always @ (A or B or control)...

CL: ALU (3/4) endcase // case(control) reg [31:0] result, C; always @ (A or B or control) begin case (control) 3'b000: // AND result=A&B; 3'b001: // OR result=A|B; 3'b010: // add result=A+B; 3'b110: // subtract result=A-B; 3'b111: // slt result=(A<B)? 1 : 0; endcase // case(control) end // always @ (A or B or control) assign zero = (result==0); endmodule // ALU Unsigned compare! Can you fix it?

CL: ALU (4/4) // if A and B have the same sign, // then A<B works(slt == 1 if A-B<0) // if A and B have different signs, // then A<B if A is negative // (slt == 1 if A<0) ... 3'b111: // slt begin temp = A - B; result = (A[31]^B[31]) ? A[31] : temp[31]; end

Step 2b: Components of the Datapath Combinational Elements Storage Elements Clocking methodology

Storage Element: Idealized Memory Write Enable Address Memory (idealized) One input bus: Data In One output bus: Data Out Memory word is selected by: Address selects the word to put on Data Out Write Enable = 1: address selects the memory word to be written via the Data In bus Clock input (CLK) The CLK input is a factor ONLY during write operation During read operation, behaves as a combinational logic block: Address valid => Data Out valid after “access time.” Data In DataOut 32 32 Clk The last storage element you will need for the datapath is the idealized memory to store your data and instructions. This idealized memory block has just one input bus (DataIn) and one output bus (DataOut). When Write Enable is 0, the address selects the memory word to put on the Data Out bus. When Write Enable is 1, the address selects the memory word to be written via the DataIn bus at the next clock tick. Once again, the clock input is a factor ONLY during the write operation. During read operation, it behaves as a combinational logic block. That is if you put a valid value on the address lines, the output bus DataOut will become valid after the access time of the memory. +2 = 35 min. (Y:15)

Verilog Memory for MIPS Interpreter (1/3) //Behavioral modelof Random Access Memory: // 32-bit wide, 256 words deep, // asynchronous read-port if RD=1, // synchronous write-port if WR=1, // initialize from hex file ("data.dat") // on positive edge of reset signal, // dump to binary file ("dump.dat") // on positive edge of dump signal. module mem (CLK,RST,DMP,WR,RD,address,writeD,readD); input CLK, RST, DMP, WR, RD; input [31:0] address, writeD; output [31:0] readD; reg [31:0] readD; parameter memSize=256; reg [31:0] memArray [0:memSize-1]; integer chann,i;

Verilog Memory for MIPS Interpreter (2/3) integer chann,i; always @ (posedge RST) $readmemh("data.dat", memArray); always @ (posedge CLK) if (WR) memArray[address[9:2]] = writeD; always @ (address or RD)* if (RD) readD = memArray[address[9:2]]; endmodule // write if WR & positive clock edge (synchronous) // read if RD, independent of clock (asynchronous) See how sneaky sensitivity lists can be! Use an assign!

Why is it “memArray[address[9:2]]”? Our memory is always byte-addressed We can lb from 0x0, 0x1, 0x2, 0x3, … lw only reads word-aligned requests We only call lw with 0x0, 0x4, 0x8, 0xC, … I.e., the last two bits are always 0 memArray is a word wide and 28 deep reg [31:0] memArray [0:256-1]; Size = 4 Bytes/row * 256 rows = 1024 B If we’re simulating lw/sw, we R/W words What bits select the first 256 words? [9:2]! 1st word = 0x0 = 0b000 = memArray[0]; 2nd word = 0x4 = 0b100 = memArray[1], etc.

Verilog Memory for MIPS Interpreter (3/3) end; always @ (posedge DMP) begin chann = $fopen("dump.dat"); if (chann==0) $display("$fopen of dump.dat failed."); $finish; end for (i=0; i<memSize; i=i+1) $fdisplay(chann, "%b", memArray[i]); end // always @ (posedge DMP) endmodule // mem // Temp variables chan, i

Storage Element: Register (Building Block) 32-bit Register Similar to the D Flip Flop except N-bit input and output Write Enable input (CE) Write Enable: negated (or deasserted) (0): Data Out will not change asserted (1): Data Out will become Data In Write Enable Data In Data Out N N Clk As far as storage elements are concerned, we will need a N-bit register that is similar to the D flip-flop I showed you in class. The significant difference here is that the register will have a Write Enable input. That is the content of the register will NOT be updated if Write Enable is not asserted (0). The content is updated at the clock tick ONLY if the Write Enable signal is asserted (1). +1 = 31 min. (Y:11)

Verilog 32-bit Register // Behavioral model of 32-bit Register: // positive edge-triggered, // synchronous active-high reset. module reg32 (CLK,Q,D,RST); input [31:0] D; input CLK, RST; output [31:0] Q; reg [31:0] Q; always @ (posedge CLK) if (RST) Q = 0; else Q = D; endmodule // reg32