XC9500XL New 3.3v ISP CPLDs

XILINX Products XILINX CPLDs FPGAs Software SPROMs Cores HardWire Hi-Rel CPLDs Xilinx offerings an entire host of PLDs solutions, including CPLDs. The FastFLASH products now have a new family to include in their product portfolio -- the XC9500XL. These new 3.3V ISP CPLDs are Flash-based and now complement a total 3.3v PLD solution for our customers. XC9500XL XC9500

Total Product Life Cycle Support Intuitive, Productive Design Flows High-Performance ISP ISP/JTAG for Manufacturing, Test & Field Upgrades Flash Technology for Highest Programming Reliability Lowest Cost Proto- typing Field Upgrades Manufacturing/Test Product Life Cycle The same, basic credo exists for the entire FastFLASH family -- provide the user with TOTAL PRODUCT LIFE CYCLE SUPPORT. And do it better than any other CPLD supplier! Every step of the cycle is supported with the best features: 1. Software that has easy, intuitive flows 2. High speed ISP (4ns/200MHz) 3. ISP/JTAG that’s designed for every step of the cycle 4. The best and latest technology, Flash, which addresses the field upgrade and overall reliability issues better than older EEPROM technology 5. A resulting cost structure which is the lowest in the industry, giving our users the best prices and value of any CPLD.

XC9500XL Key Features High performance 36 to 288 macrocell densities tPD = 4ns, fSYS = 200MHz 36 to 288 macrocell densities Highest programming reliability 10,000 program/erase cycles Most complete IEEE 1149.1 JTAG support Space-efficient packaging, including chip scale pkg Industry’s first 0.35um Flash CPLD This lists the major, key features of the new 9500XL product family. Focus on the speed leadership. Also, point out that by using Flash technology, we can offer the best programming reliability (key for 50% of the CPLD applications today -- FIELD UPGRADES) as well as the lowest cost. CSP is leadership and only Xilinx has the 0.8mm ball-to-ball spacing. More on this in a later slide.

XC9500XL Architecture Embraces In-System Changes Advanced, 2nd Generation Pin-Locking Superior routability with speed Maximum Flexibility 54-input function block fan-in 90 p-terms per output 3 global, locally invertible clocks global set/reset pin p-term OE per macrocell clock enable The XC9500XL architecture is an enhancement of the popular XC9500 architecture, considered by many to be the most flexible architecture on the market-- for accommodating unexpected in-system changes! Pin-locking continues to improve, with the XL incorporating an even better pin-locking performance. This comes as a result of an enhanced interconnect, more inputs to the function block and significantly enhanced routing software. To make the 9500XL family THE most flexible (I.e., best at accommodating design changes while improving speed), we’ve provided this long list of industry leading architecture features. Especially key are the 54 function block inputs. The increase (with the 9500 having 36 inputs) provides more inputs to the function block, better overall utilization and better pin-locking. Only XILINX has 54 function block inputs! 5

XC9500XL System Features I/O Flexibility Input hysteresis on all pins 5v tolerant; direct interface to 3.3v & 2.5v Input hysteresis on all pins User programmable grounds Bus hold circuitry for simple bus interface Easy ATE integration for ISP & JTAG fast, concurrent programming times This list itemizes all the great system features that are available on the XC9500XL as is specifically targeted at meeting the system designer’s needs. Each feature is designed to help the actual application of incorporating a CPLD onto the system board.

New XC9500XL 3.3V Family XC9536XL XC9572XL XC95144XL XC95288XL Macrocells 36 72 144 288 Usable Gates 800 1600 3200 6400 tPD (ns) 4 5 5 6 fSYSTEM 200 178 178 151 Packages (Max. User I/Os) 44PC (34) 64VQ (36) 48CS (36) 44PC (34) 64VQ(52) 100TQ (72) 48CS (38) 100TQ (81) 144TQ (117) 144CS (117) 144TQ (117) 208PQ (168) 352BG (192) The family is planned with 4 devices in the most popular macrocell densities. Note the full complement of pin-compatible package options. Each package has list in parenthesis the actual number of I/Os. Easy density migration is available for all like packages. This lowers the users risk when his/her design grows. World class speed spec’s reflect the key attribute of this new 3.3V ISP family. Only Xilinx offers a 4ns tpd and system cycle speeds of 200MHz. The family will become available starting 2H98, beginning with the XC95144XL. After that, the ‘72XL and ‘36XL will become available in end Q4C98. The 95288XL will be available in Q1C99. BGA CSP 9

XC9500XL Supports High-Speed Applications Fast decode logic DSP, SDRAM, CPU High-frequency state machines bus arbiter, data path controller Leading-edge systems networking graphics workstations With the highest speeds, these leading edge applications become possible. 4

Most Complete JTAG Testability IEEE Std 1149.1 boundary-scan testability & advanced system debug/diagnosis 8 instructions supported (incl. CLAMP) Full support on all family members Industry-standard ISP interface Complete 3rd party support The XC9500XL family has the most complete, industry-standard JTAG boundary-scan capabilities -- supporting an important capability for all new system designs. In addition to manufacturing test benefits, JTAG boundary-scan enhances development and debug as well, especially in complex, tightly packed systems. JTAG allows all internal nodes to be read out using only the 4 JTAG pins! The XC9500XL (along with XC9500) is the only CPLD family to support full JTAG boundary-scan in the whole CPLD family -- even lower density devices! The JTAG-based in-system programming (ISP) protocol allows compliance with emerging standards, such as the IEEE 1149.1 subcommittee formalizing a standard for ISP. 6

Chip Scale Packaging Leadership Supports high-growth market segments: Communications, Computers, Consumer New 48-pin CSP: 1/3 size of the VQ44 Xilinx has lead the industry again with the introduction of the small, space-efficient Chip Scale Package. The CSP solution is available on the 36XL/72XL and 144XL. The smaller package makes it ideal for applications that require programmable logic in the smallest footprint possible. Uses standard IR techniques for mounting to PC board

Productive Implementation Flow for CPLDs Simplified Project Management Implementation Templates for Speed & Density Push Button Design Flows USER BENEFITS Faster Clock Speeds Higher Device Utilization optimized logic/cm2 Industry’s Best Pin-Locking more design flexibility, less risk, lower cost The new v1.5 software provides CPLD designers with one of the industry best design flows available today. From the simple project manager, to the ready-built speed and density templates, and the push-button design flow manager, Xilinx CPLD software provides the designer with an excellent solution. These enhancement apply to both Foundation and Alliance software solutions from Xilinx.

Xilinx CPLD Process Leadership Non-Volatile Year used in Year used in SPLD/CPLD Technology Memories SPLD/CPLD Pioneer Bipolar Fuse 1973 1978 MMI (AMD) EPROM 1979 1984 Altera EP-series 5V EEPROM 1986 1991 Lattice ispLSI 5V FLASH 1990 1995 Xilinx XC9500 With each change in non-volatile technology comes a new application and also a new product leader. With bipolar fuse technology, MMI lead the way in SPLDs. With the invent of EPROM memory technology, Altera applied it to CPLDs and quickly became the CPLD leader (still applies today). When 5V EEPROM memory technology was introduced, 5 years later Lattice applied it well to ISP CPLDs. But times and technologies have moved on. XILINX saw this change and was the first PLD vendor to move to 5v ISP Flash technology. Based on the technology trends of the past, plus the significant benefits of Flash both in memories and logic, XILINX is perfectly positioned to become the next leader in CPLDs. 3.3V FLASH 1993 1998 Xilinx XC9500XL

Xilinx Has Fastest CPLDs with Smallest Die Size True 3.3V 0.35µm Small Die (0.35µm metal) Degraded 5V Inefficient 3.3V Large Die Lattice ispLSI2000V Altera Max7000A Only the Xilinx Flash-based CPLD products are TRUE 0.35 micron technology. Competitive CPLDs aren’t really true 0.35 micron, as the graph shows, and results in either a larger die (weakens their cost competitiveness) or slower speeds (lose out at fast system designs). Lattice die are 0.5 micron drawn from a derated 5v part yielding a very slow 3.3v device. Vantis devices are faster than Lattice but their metal technology (0.5 micron) makes for a large, expensive die. Altera is the next fastest 3.3V device but they too have larger metal technology, resulting in a big die. The Xilinx 0.35 micron Flash process includes both gate length and metal dimensions, something that none of the other CPLD vendors can match. The result is that Xilinx has the smallest 0.35 micron die which provides the lowest cost solution as well as supporting the fastest device speeds. (0.5µm metal) Vantis Mach5LV Slow Fast (0.5µm drawn length) (0.35µm drawn length)

Xilinx Lowering Cost Across The Supply Chain LEADING EDGE TECHNOLOGY STREAM-LINED OPERATIONS “MEMORY STYLE” MANUFACTURING 1st with Flash ISP Only true 0.35um Apply memory R&D advantages to CPLDs Long-term foundry agreements Stream-lined device/pkg offerings High volume packages 10ns slowest speed grade Off-shore sort, test and assembly Multi-site parallel test Fast time-to-market Xilinx has a very aggressive supply chain management program aimed at reducing cost, providing high volumes of product, in the right product options. Our Flash technology benefits are numerous and proven out by all the major memory vendors today. Operations are streamlined for efficiency and our manufacturing flow is set up very much like the way memories are handled today. All this supports our strategy of providing the most cost efficient CPLD in the industry. 9

New Price Points Open Up New CPLD Applications Motherboards for PCs and servers PC peripherals and add-on cards DVD players/controller cards Graphics cards Automotive Engine control Automotive navigation systems (GPS) Consumer Coffeemakers Video Games/Toys These new cost points, supported by our technology and supply chain management strategies, allow users that haven’t designed with CPLDs previous now to do so. Densities, ease-of-use and now lower prices make CPLDs the logic of choice for almost every cost sensitive application.

XC9500XL The Complete CPLD Solution Product Life Cycle Support Flexible 3.3v ISP Architecture New Leadership Features Productive Software Lowest Cost Solution Today, Xilinx has moved from a supplier of CPLDs to a position of leadership in both 3.3v and 5v CPLDs. Lead by the XC9500XL 3.3v ISP CPLDs, and together with our software, Xilinx provides logic users the industry’s best SOLUTION today.

XC9500XL Appendix

3.3V ISP CPLD Comparison 32 to 288 Macrocells Xilinx XC9500XL Altera Max7000AE Lattice isp2000V Vantis Mach4LV Description Macrocell range (<= 288) Number of user I/O pins Best tPD Best fMAX Architecture Maximum block fan-in Max p-terms/macrocell Local clock inversion Individual OE per output Reliability Endurance Rating (cycles) Data Retention (years) Process Technology 36 - 288 34 - 192 4ns 200MHz 54 90 Yes 10,000 20 yrs FLASH 32 - 256 36 - 164 5ns 178MHz 36 32 No 100 10 yrs EEPROM 32 - 128 35 - 138 7.5ns 100MHz 18 20 No 10,000 20 yrs EEPROM 32 - 256 34 - 142 7.5ns 125MHz 34 20 No 100 10 yrs EEPROM 62

FastFLASHTM 3.3V Die Size Leadership Max7128A 128 Macrocells EEPROM XC95144XL 144 Macrocells FLASH 1.0x* 1.18x* * Factor based on per macrocell comparison

Leadership CPLD Pricing Device Macrocells Price Price/MC XC9536XL 36 $ 1.20 $0.03 XC9572XL 72 $ 1.85 $0.03 XC95144XL 144 $ 5.65 $0.04 XC95288XL 288 $11.95 $0.04 Note: Pricing for 100,000 unit quantities in mid-1999