aUniversità degli Studi di Pavia Dipartimento di Elettronica ciao CMOS processes in the 100 nm minimum feature size range for applications to the next generation collider experiments L. Rattia,c, M. Manghisonib,c, V. Reb,c, V. Spezialia,c, G. Traversib,c aUniversità degli Studi di Pavia Dipartimento di Elettronica bUniversità degli Studi di Bergamo Dipartimento di Ingegneria Industriale cINFN Sezione di Pavia saluti

Motivation Use of CMOS microelectronic processes in the last two decades has had a deep impact on the way HEP instrumentation is conceived Quarter micron technology able to comply with the challenging design requirements of the LHC experiments in terms of noise figure power dissipation radiation tolerance Luminosity and track densities expected at the next generation colliders (LHC upgrade, ILC, Super B-Factory) set the demand for increased spatial resolution, denser functional packing, higher radiation hardness and better noise/power trade-off HEP people is considering moving to more scaled CMOS processes Technology monitoring to keep design criteria and methodologies up to date fight process obsolescence study scaling down effects on the main design parameters

Investigated technologies and devices Single transistors from HCMOS9 130 nm and CMOS090 90 nm triple well, epitaxial CMOS technologies by STMicroelectronics HCMOS9 (Lmin=130 nm) CMOS090 (Lmin=90 nm) Technology features: VDD = 1.2 V tOX= 2 nm COX=15 fF/μm2 Available geometries W = 200, 600, 1000 μm L = 0.13 - 1 μm Technology features: VDD = 1 V tOX= 1.6 nm COX=18 fF/μm2 Available geometries W = 100, 200, 600, 1000 μm L = 0.1 – 0.7 μm Devices under test are PMOS and NMOS transistors with standard open layout

Operating region Drain current in DUTs: from tens of mA to 1 mA  low power operation as in high density front-end circuits μ carrier mobility COX specific gate oxide capacitance VT thermal voltage n proportional to ID(VGS) subthreshold characteristic Characteristic normalized drain current I*Z may provide a reference point to define device operating region

Operating region Inversion coefficient At the considered drain currents, DUTs work in weak or moderate inversion region At a given drain current, operation is shifted towards weak inversion region with technology scaling

Transconductance At small ID (weak inversion), gm fairly independent of the device dimension and polarity In weak inversion, possible difference between PMOS and NMOS and between CMOS nodes only due to different n values (n1.25 for both polarities and technologies considered here)

Noise in CMOS transistors Noise in the drain current of a MOSFET can be represented through an equivalent noise voltage source in series with the device gate SW - white noise channel thermal noise (main contribution in the considered operating conditions) other contributions from parasitic resistances S1/f - 1/f noise technology dependent contribution both kf and αf depends on the polarity of the DUT kf 1/f noise parameter αf 1/f noise slope-related coefficient kB Boltzmann’s constant T absolute temperature αw excess noise coefficient γ channel thermal noise coefficient

Noise in different CMOS generations 250 nm TSMC 130 nm STM 90 nm STM

Noise vs gate length – STM 130 nm High frequency, white noise virtually independent of the gate length L, in agreement with gm behavior 1/f noise contribution decreases with increasing channel length, as predicted by the noise equation

Noise vs drain current - NMOS High frequency, white noise decreases with increasing drain current in both technologies, in agreement with gm behavior 1/f noise contribution is to a large extent independent of the drain current

Noise vs drain current - PMOS High frequency, white noise decreases with increasing drain current, more markedly so in the 90 nm technology 1/f noise contribution increases with increasing current, more significantly in the STM 130 nm technology

Noise and inversion region At low drain current both devices work in the weak inversion region  channel thermal noise is roughly the same for both devices At high drain current, a significant difference in the channel thermal noise can be detected  device from the 90 nm technology works closer to weak inversion region Better 1/f noise performance provided by the STM 90 nm technology

Channel thermal noise – STM 90 nm Equivalent channel thermal noise resistance slope  excess noise coefficient aw offset  noise contributions from parasitic resistors aw close to unity  no sizeable short channel effects in the considered operating regions (no data available for channel thermal noise in devices with L ≤0.13 mm) Negligible contributions from parasitic resistances

Channel thermal noise – STM 130 nm αw close to unity  no sizeable short channel effects in the considered operating regions also for STM 130 nm technology (except for NMOS with L=0.13 mm) Negligible contributions from parasitic resistances in NMOS devices, larger in PMOS transistors  possibly due to different doping levels used in critical layers

Flicker noise Slope af of the 1/f noise term is significantly smaller than 1 in NMOS transistors and larger than 1 in PMOS devices

Slope coefficient af In the examined operating region, af does not exhibit any clear dependence on the drain current or on the channel length af between 1 and 1.3 for PMOS devices, between 0.8 and 1 for NMOS devices

Slope coefficient af Very similar behavior of af was detected through different CMOS generations and different foundries

1/f noise coefficient kf vs gate length In the case of the 130 nm technology, short channel devices (L<0.5 mm) exhibit a flicker noise coefficient larger than for NMOSFETs with longer channels The same behavior concerns devices with L<0.2 mm in the case of the 90 nm technology

1/f noise coefficient kf vs Vov In PMOS devices, flicker noise coefficient is clearly bias dependent (dependence is weaker in STM 90 nm technology) In NMOS transistors kf is to a large extent independent of the overdrive voltage VOV

60Co g-rays effects on device performances ID increase in the subthreshold region of NMOS: edge effects due to radiation-induced charge at the shallow trench isolation (STI) oxide. The effect is larger in devices with a shorter channel, affecting ID regions of interest for low-power applications (ID = 100 mA). 0.13 µm technology (open-structure layout)

60Co g-rays effects on device performances In short-channel NMOS, at low ID (around 100 mA) 1/f noise increases by a much larger extent than at higher drain currents. This may be correlated with the ID increase in the subthreshold region, meaning that the shallow trench oxide contributes in determining the 1/f noise properties of irradiated open-structure devices.

Conclusions Static, signal and noise measurements have been performed on devices belonging to two different CMOS technology nodes, namely the 130 nm and 90 nm STM processes Channel thermal noise equations developed to describe the device behavior in the considered operating regions provide a reliable model, with short channel effect playing a minor role in both the considered processes 1/f noise results confirm the behavior detected in previous submicron processes as far as the dependence on device polarity and bias and gate geometry is concerned Extracted noise parameters show that using the 90 nm process may ensure an improvement in the noise performances in applications where large signal dynamic range is not needed while miniaturization can be an asset Characterization of the 90 nm technology will be completed with radiation hardness tests (open structure vs enclosed layout, study of possible STI effects)

Backup slides

Channel thermal noise coefficient

Low noise charge preamplifier design Circuit designers can take advantage of single device characterization to predict noise behavior of charge sensitive amplifiers Equivalent noise charge is the figure of merit to be minimized: CD detector capacitance CG preamplifier input capacitance tp peaking time A1 A2 shaping coefficients Channel thermal noise contribution Flicker noise contribution Data extracted from single transistor characterization can be used to plot minimum ENC as a function of the main design parameters (peaking time, power dissipation, polarity and dimensions of the preamplifier input device) It is interesting to assess whether (and if so to what extent) using a more scaled technology may improve noise performances

ENC vs peaking time ENC was evaluated in the case of a second order, unipolar (RC2-CR) shaping processor In the explored peaking time and power range, PMOS input device always provides better noise performances than NMOS input (except for the 130 nm process at tp close to 10 ns) Using the 90 nm process may yield quite significant improvement with respect to the 130 nm technology, especially when NMOS input charge preamplifiers are considered

ENC vs dissipated power At tp=20 ns, noise performances provided by NMOS and PMOS input devices in the 90 nm technology are comparable Better noise-power trade-off can be achieved by using the 90 nm technology

Transconductance in all inversion regions