Interconnect Architecture

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Presentation transcript:

Interconnect Architecture Chung-Kuan Cheng Computer Science and Engineering Department University of California, San Diego

Interconnect Architecture Wire Directions (M, Y, X, E) Layout Region (M, D, Y, X) Power Ground and Clock Distributions Layer Assignment Via Arrangement Comparison Wire Length Throughput Grid vs No-grid

7 by 7 meshes with different interconnect architectures 1. Wire Directions and Models (a) A 7 by 7 mesh with Y-architecture (b) A 7 by 7 mesh with Manhattan-architecture (c) A 7 by 7 mesh with X-architecture 7 by 7 meshes with different interconnect architectures

2. Layout Regions and Models (a) A level 2 hexagonal mesh (b) A level 2 octagonal mesh (c) A level 2 Diamond mesh Fig. 10 Meshes with symmetrical structures

Length of 2 pin-nets to extend an area Shape Man. Y-Arch X-Arch Euclidean M: Diamond 1.250 1.118 1.066 1.014 Y: Hexagon 1.101 X: Octagon 1.055 E: Circle 1.273 1.103 1.000 E (worst) 1.412 1.155 1.082

Throughput : concurrent flow demand Shape Manhattan Y-Arch X-Arch* M: Square 1.000 1.225 1.346 M (Bound) 1.241 1.356 M: Diamond 1.195 Y: Hexagon 1.315 X: Octafon 1.420 *ratio of 0-90 planes and 45-135 planes is not fixed

Flow congestion map for uniform 90 Degree meshes

Congestion map of square chip using X-architecture 12 by 12 13 by 13

Congestion map of square chip using Y-architecture 12 by 12 13 by 13

Explanation For Throughput Increasing Number of lines across the vertical center cut-line: d/D for 90 degree routing for 45 degree routing

Y-Architecture X-Architecture Global Grids (Power/Ground Mesh) (http://www.xinitiative.org/img/062102forum.pdf)

3. Clock Tree on Square Mesh N-level clock tree: path distance = 21% less than H-tree total wire length = 9% less than H tree, 3% less than X tree No self-overlapping between parallel wire segments

4. Layer Assignment Different routing direction assignment Layer 4 IV Assignment I II III Different routing direction assignment

N z(I) z(II) z(III) z(IV) 5 1.02 0.83 1.01 6 0.97 0.73 0.74 7 0.94 Normalized throughput of mixed 45-degree and 90-degree mesh with different routing layer assignments N z(I) z(II) z(III) z(IV) 5 1.02 0.83 1.01 6 0.97 0.73 0.74 7 0.94 0.71 0.93 8 0.90 0.69  

Why interleaving Manhattan Layer and Diagonal Layer Improves Throughput? (0,3) Wirelength = 3.82 Wirelength = 5.0 (2,0) Shortest path between two points on the plane are always a concatenation of a Manhattan line and a Diagonal line.

Observations Routing Direction Assignment Strategies Can Affect the Communication Throughput. Interleaving the Manhattan Routing Layers and Diagonal Routing Layers can produce better Throughput

5. Via Arrangement: Banks and Tunnels Use tunnels to detour around vias Use banks of tunnels to maximize the throughput Use bottom k layers to perform intra-cell routing Use top n-k layers to distribute signals to the banks

Via-Oriented Interconnect Planning

Via-Oriented Interconnect Planning tunnel

Via-Oriented Interconnect Planning Bank of tunnels k+2 overhead Full bandwidth #vias= kL Overhead=k+2 vertical Tracks L: dimension of the bank

Tunnel of Y Arch. Blocking 5 tracks on the layer of 60-degree direction

Tunnels of Y Arch.

3.2 Via-Oriented Interconnect Planning #vias= c1kL Bank of tunnels Overhead= k+c2 tracks

Conclusion Modeling and Analysis: Multi-commodity Flow Package Layout: Placement and Routine Technology and Electrical Circuit Analysis