Physics of Semiconductor Devices （4.5~4.6） Department of Optical Engineering Liu Zuanjie

4.5 DESIGN OF PRACTICAL POLYSILICON EMITTER TRANSISTORS Current gains of 1000 or more can easily be realized in a device with a deliberately grown interfacial layer ,but only at the cost of increased emitter resistance .At sub-micron geometry it could be large enough to significantly degrade circuit performance . Three important parameters: current gain emitter resistance emitter/base capacitance(Chapters6&7)

4.5.1 Structure of the Polysilicon/Silicon Interface Three processing variables have the greatest effect on the surface . These three processing variables: suface treatment, emitter implant dose , drive-in temperature The last figure illustrates the influence of the suface treatment for a device given a drive-in at 900 an emitter implant of1 When a wet chemical surface treatment is given ,a continuous and uniform interfacial layer is obtained. When an etch in HF acid is given,a much thinner , discontinuous interfacial layer is obtained.In some places there are holes ,small areas of polysilicon have regrown through the holes.

The Inflluence of the Emitter Drive-in Temperature The influence of the emitter drive-in temperature is illustrated in the figure for a device given an RCA clean prior to polysilicon deposition. Drive-ins at temperature of 925 or below have no effect on the nterfacial oxide,and hence a continuous ,uniform layer is obtained,as shown in fig (a). Drive-ins at 950 and higher lead to the break-up of the interfacial layer. The driving force for the break-up is believed to be minimization of the energy associated with the oxide/silicon interface.

The influence of the break-up on the electrical characteristics of the transistors is shown in Fig.4.16 The results in Fig.4.16 shows that the progressive break-up of the interfacial layers leads directly to an increase in the base current and hence a decreasein the current gain.

Conclusion： Problems: The polysilicon/silicon interface can be engineered to give different combinations of emitter resistance and current gain. for example,if high gains are of paramount importance then the process should include an RCA treatment ,the polysilicon should not be heavily doped and the emitter drive-in should be carried out at a temperature of 900 Problems: device modelling: empirical approach:average effective recombination velocity at the surface. reproducibility: problems of batch-to-batch advance variability are likely to be encountered unless the interface treatment and the polysilicon deposition conditions are very tightly controlled.

4.5.2 Structure of the Polysilicon Layer The main process variables: polysilicon thickness ,polysilicon deposition temperature ,dopant concentration ,emitter dopant type polysilicon deposition temperature:≤580，amorphous silicon ;＞580，polycrystalline silicon dopant concentration:high concentration of dopant leads to an enhancement of grain growth during the emitter drive-in. emitter dopant type:phosphorus give lager grains and lower resistances than an equivalent amount of arsensic .

polysilicon thickness: the polysilicon thickness has little effect on the current gain,this is becaus the pseudo -grain boundary at the polysilicon/silicon interface dominates over the grain boundaries in the polysilicon.

4.5.3 Diffusion in Polysilicon Arsenic diffusion in polysilicon emitters occurs in two distinct stages .the first is rapid diffusion down the boundaries and the second is slow diffusion into the bulk of the grains and into the single-crystal emitter.the second stage occurs at a very low rate ,and hence makes possible good control over the depth of the emitter/base junction. .

arsenic which is segregated at grain boundaries is generally electrically inactive

4.6 SIS EMITTERS One of the reasons that polysilicon emitters are so usefull in high-speed bipolar process is that very shallow emitter/base jucctions can be realized .In the limit ,the junction depth of a polysilicon emitter can be reduced to zero simply by lowering the temperature fo the emitter drive-in .The electrical characteristics of this type of device bear a close resemblance to those of MIS devices,and for this reason will be referred to here as an SIS emitter.

There is a band-bending at the surface of the p-type base region There is a band-bending at the surface of the p-type base region.Accurate modelling of the SIS emitter requires: Direct tunnelling through the interfacial layer JnT and JpT. Tunnelling between the valence band and surface states Jptrap,and between the conduction band and surface states Jntrap; Shockley-Read-Hall recombination on the single-crystal side of the interfical layer Jprec and Jnrec. Equations describing these mechanisms know be specified and solved numerically for the base current as a function of base/emitter voltage.

Typical electrical results for practical SIS emitters are shown in the left figure ,along with comparable results for polysilicon emitters. At low forward biases (<0.7V) the band-bending at the silicon surface is sufficiently large that the surface is inverted to n-type. As the forward bias is increased the band-bending at the silicon surface progressively reduces until the surface moves out of inversion to become p-type. It is this transition of the surface from n- to p-type that defines of the onset of the kink region.

In the kink region (0.9~1.0V) the base characteristic is controlled by two competing factors: the supply of electrons from the polysilicon and the band bending at the surface. At high forward biases (>1.1V) the direct hole tunnelling current JpT ,which increases monotonically with applied bias, comes to dominate the base characteristic. In general ,SIS emitters are inferior to polysilicon emitters because they do not provide as much collector current at a given base /emitter voltage. The current gain is also highly current-dependent ,decreasing rapidly at low currents due to the non-ideal base characteristic. There is therefore a practical limit to the extent that the emitter /base junction depth of a polysilicon emitter transistor can be reduced ,and this determined by the onset of SIS behavior

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