MOS Capacitor Basics Metal SiO2 G SiO2 Sub Metal Note that there is not a DC current between the gate, G, and the substrate, sub, since SiO2 is almost a perfect insulator.

Band-diagram Band-bending approximation assumes that the “local” mobile carrier densities are govern by local EC , EV , EF . This assumption is only valid if the electrostatic potential variation is not too rapid, which is true in the case for MOS.

Accumulation E C V FS FM Þ more electrons at interface

Depletion nS and pS are both small E FM C FS V + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + nS and pS are both small

Inversion Near the surface Þ a lot of holes there E FM C FS V + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Near the surface Þ a lot of holes there

Since there is no current flow, Just need to solve Poisson’s equation. Assumptions:

Definition of terms

We define the potential via At the interface of Si and SiO2 (i.e. x=0 ) For x=¥, i.e. deep into the bulk silicon

We also define the band-bending At the Si/SiO2 interface: Dimensionless potential and band-bending: Note we also define

Therefore Now, when x­¥, i.e., or

Poisson’s equation With all the assumptions mentioned previously: But With

i.e., Poisson’s equation can be written as: where Now, since we have

Þ Integrate once to obtain:

Note that where is the surface electric field.

Solving the integration, we have: where is the electric field i.e.

where sgn is the sign function: Defining a dimensionless electric field at the surface:

We can obtain u(x) by solving: where i.e. Can slove this numerically.

Depletion Approximation Actual case Depletion Approx WD Recall that depletion approximation is good, except within an extrinsic Derby length around x=WD.

Using the same assumptions as before, we can solve the Poisson’s Equation using Depletion approximation: We can get f by integrating one more time, but it is easier to deal with y in this case.

First, remember that since y and f differ only by a constant, fB

Maximum Depletion Width

The field due to the inversion charge can be approximated by: In other word, we can approximate:

Again WD occurs when In case of n-type substrate, inversion occurs when With

An approximated solution is

When VS=VL, WD = WDmax . WDmax with depletion approximation is given by for n-substrate for p-substrate where ln and lp are the extrinsic Derby lengths:

Note that the E-field in the oxide is related to the semiconductor E-field at x=0 via if there is no interface charge Also if there is no charge in SiO2 Therefore, we can solve the potential from the terminal characteristics by:

Gate Currents in MOSFET with Thin Oxide Historically, EOT follows the relationship:

The relationship is no longer true starting from the 130nm node due to difficulty in oxide scaling: Direct tunneling currents NBTI and other oxide reliability “running out of SiO2 molecules” to reduce EOT. Tunneling current is most sensitive to the oxide thickness. As the thickness of the oxide layer decreases, the tunneling current increases exponentially. This increased current, not only adversely affects the MOS device performance but also significantly increases the standby power consumption of a highly integrated circuit.

When a large positive bias is applied to the gate electrode, electrons in the strongly inverted surface can tunnel into or through the oxide layer and hence give rise to a gate current. Similarly if a large negative bias is applied to a heavily doped n+ poly gate, electrons from the n+ poly Si can tunnel into or through the oxide layer.

I. Fowler-Nordheim Gate Tunneling: Fowler-Nordheim tunneling is the process when electrons from the silicon surface inversion layer tunnel into the conduction band of the oxide via a triangular barrier. Fowler-Nordheim

Direct tunneling of carriers: Channel conduction band into Gate (CBET) II. Direct Tunneling. k Direct tunneling of carriers: Channel conduction band into Gate (CBET) Channel valence band into Gate (VBET) Holes from the valence band in the n+ poly gate into the p-substrate (VBHT)

Direct tunneling current can be modeled by: B and C are physical parameters that take into account the voltage dependence of the densities of states at the electrode interface and the effective masses in the oxide. Also

The tunneling current is typically derived using Bardeen’s transition probability approach and Harrison’s independent particle tunneling model. The result is the following expression: The theory and the experimental data agrees very well.

In order to reduce gate leakage due to direct tunneling and to allow scaling of EOT below 1nm, alternative gate dielectric which has higher dielectric constant and can increase Cox even with physically thicker film will be required. EOT for high-k (high relative dielectric constant) materials is defined by: where k is the high-k material dielectric constant.

The requirements of high-k dielectrics for MOSFETs are: EOT scalability < 10Å Dielectric constant > 15 Negligible FIBL effect Dielectric constant < 60 Leakage current < 1A/cm2 Bandgap > 5eV, Barrier height > 1eV Thermal stability No silicidation and reduction Hysteresis < 20mV Fixed Charge density Interface state density < 1011/eVcm2 Mobility similar to that of SiO2 Reliability >10 years

Tunneling depends on both the tunneling width as well as the barrier height. There appears an relationship between Band-gap and k-value. Question: How does tunneling currents behave using high-k dielectrics with the same EOT?

But: It is not EG that matters, but fB!

Going over the requirements list, it appears that ZrO2 and HfO2 are good candidates.

How about the tunneling currents of these high-k materials since fB is only ~1.5V? Å Experimentally, it is found that the gate leakage is much smaller for high k-dielectrics!

However, mobility is slightly smaller than SiO2 devices. It is generally believed that the reduction in mobility is caused by remote charge scattering from the charges at the High-K/metal interface.

It is important to know that EOT is not the only parameter that matters. tdielectric is also important. Note that as k goes up, tdielectric goes up for the same EOT and SCE becomes worse.

Examination of the 2-dimensional electric field distribution indicates that the short-channel performance degradation is due to the fringing fields from the gate to the source/drain regions. The thicker gate (k = 50) has weaker control over the channel because more of the electric field lines terminate in the source/drain regions. In fact, he subthreshold swing has a 10% degradation when the high-k (k = 37) dielectric thickness to the gate length (Tk/LGate, not Tk/Leff) ratio reaches 1/5.