CPE 528: Lecture #4 Department of Electrical and Computer Engineering University of Alabama in Huntsville.

Slides:

Advertisements

Similar presentations

Introduction to VHDL CLASS MATERIALS EECE 255. Very High Speed Integrated Circuit Hardware Description Language Industry standard language to describe.

Advertisements

1 Lecture 13 VHDL 3/16/09. 2 VHDL VHDL is a hardware description language. The behavior of a digital system can be described (specified) by writing a.

VHDL ELEC 418 Advanced Digital Systems Dr. Ron Hayne Images Courtesy of Thomson Engineering.

Introduction to VHDL (Lecture #5) ECE 331 – Digital System Design The slides included herein were taken from the materials accompanying Fundamentals of.

Comprehensive VHDL Module 6 Types November Comprehensive VHDL: Types Copyright © 2000 Doulos Types Aim ©To understand the use and synthesis.

VHDL Data Types Module F3.1. VHDL Data Types Scalar Integer Enumerated Real (floating point)* Physical* Composite Array Record Access (pointers)* * Not.

The IEEE Libraries And Examples Using Functions. Libraries Using the Library Command VHDL allows libraries defined using: library LibraryName; Here, we.

©2010 Cengage Learning Engineering. All Rights Reserved.10-0 Introduction to VHDL PowerPoint Presentation © Cengage Learning, Engineering. All Rights.

CPE 626 Advanced VLSI Design Lecture 3: VHDL Recapitulation Aleksandar Milenkovic

VHDL – Dataflow and Structural Modeling and Testbenches ENGIN 341 – Advanced Digital Design University of Massachusetts Boston Department of Engineering.

A VHDL Tutorial ENG2410. ENG241/VHDL Tutorial2 Goals Introduce the students to the following: –VHDL as Hardware description language. –How to describe.

IAY 0600 Digital Systems Design

Lecture 3 Chap 4 Types Instructors: Fu-Chiung Cheng ( 鄭福炯 ) Associate Professor Computer Science & Engineering Tatung University.

陳慶瀚機器智慧與自動化技術 (MIAT) 實驗室國立中央大學資工系 2009 年 10 月 8 日 ESD-04 VHDL 硬體描述語言概論 VHDL Hardware Description Language.

Fall 2004EE 3563 Digital Systems Design EE 3563 VHDL – Basic Language Elements  Identifiers: –basic identifier: composed of a sequence of one or more.

Lecture 4 Chap 5 Types Instructors: Fu-Chiung Cheng ( 鄭福炯 ) Associate Professor Computer Science & Engineering Tatung University.

CPE 626 Advanced VLSI Design Lecture 4: VHDL Recapitulation (Part 2) Aleksandar Milenkovic

Lecture #8 Page 1 Lecture #8 Agenda 1.VHDL : Operators 2.VHDL : Signal Assignments Announcements 1.HW #4 assigned ECE 4110– Digital Logic Design.

Copyright(c) 1996 W. B. Ligon III1 Getting Started with VHDL VHDL code is composed of a number of entities Entities describe the interface of the component.

VHDL Very High Speed Integrated Circuit Hardware Description Language Shiraz University of shiraz spring 2011.

Design Methodology Based on VHDL Instructors: Fu-Chiung Cheng ( 鄭福炯 ) Associate Professor Computer Science & Engineering Tatung University.

Electrical and Computer Engineering University of Cyprus LAB 1: VHDL.

1 Workshop Topics - Outline Workshop 1 - Introduction Workshop 2 - module instantiation Workshop 3 - Lexical conventions Workshop 4 - Value Logic System.

Lecture #7 Page 1 Lecture #7 Agenda 1.VHDL Data Types Announcements 1.n/a ECE 4110– Digital Logic Design.

Chapter 5 Introduction to VHDL. 2 Hardware Description Language A computer language used to design circuits with text-based descriptions of the circuits.

L19 – Resolved Signals. Resolved Signals  What are resolved signals In systems In VHDL Resolution – Isn’t that for resolving conflicts?  Ref: text Unit.

IAY 0600 Digital Systems Design

DATA TYPES 1.Pre-Defined Data Types 2. User-Defined Data Types.

CEC 220 Digital Circuit Design More VHDL Fri, February 27 CEC 220 Digital Circuit Design Slide 1 of 15.

CEC 220 Digital Circuit Design Introduction to VHDL Wed, February 25 CEC 220 Digital Circuit Design Slide 1 of 19.

BASIC VHDL LANGUAGE ELEMENTS Digital Design for Instrumentation with VHDL 1.

VHDL Discussion Subprograms IAY 0600 Digital Systems Design Alexander Sudnitson Tallinn University of Technology 1.

ECOM 4311—Digital System Design with VHDL

VHDL Programming Fundamentals Presented By Dr. Pradyut Kumar Biswal Department of Electronics, IIIT Bhubaneswar.

CEC 220 Digital Circuit Design Introduction to VHDL Friday, February 21 CEC 220 Digital Circuit Design Slide 1 of 10.

Lecture #8 Page 1 Lecture #8 Agenda 1.VHDL : Operators 2.VHDL : Signal Assignments Announcements 1.HW #4 assigned ECE 4110– Sequential Logic Design.

CEC 220 Digital Circuit Design Introduction to VHDL Wed, Oct 14 CEC 220 Digital Circuit Design Slide 1 of 19.

Chapter 8. Additional Topics in VHDL 권동혁.

1 CS 352 Introduction to Logic Design Lecture 5 Ahmed Ezzat Multiplexers, Decoders, Programmable Logic Devices, and Intro to VHDL Ch-9 + Ch-10.

IAY 0600 Digital Systems Design

Introduction To VHDL 홍 원 의.

Design Entry: Schematic Capture and VHDL

Operators Assignment Operators Logical Operators Relational Operators

Chapter 2. Introduction To VHDL

ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448 – FPGA and ASIC Design with VHDL.

Behavioral Modeling in Verilog

CPE 626 Advanced VLSI Design Lecture 2: VHDL Recapitulation Aleksandar Milenkovic

ECE 434 Advanced Digital System L17

ECE 434 Advanced Digital System L15

CPE/EE 422/522 Advanced Logic Design L15

ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448 – FPGA and ASIC Design with VHDL.

CHAPTER 10 Introduction to VHDL

OPERATORS and CONCURRENT STATEMENTS

ECE 434 Advanced Digital System L9

CPE/EE 422/522 Advanced Logic Design L08

CPE/EE 422/522 Advanced Logic Design L07

CPE/EE 422/522 Advanced Logic Design L14

ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448 – FPGA and ASIC Design with VHDL.

CPE/EE 422/522 Advanced Logic Design L11

ECE 434 Advanced Digital System L10

VHDL Discussion Subprograms

IAS 0600 Digital Systems Design

CPE 528: Lecture #5 Department of Electrical and Computer Engineering University of Alabama in Huntsville.

CPE 528: Lecture #3 Department of Electrical and Computer Engineering University of Alabama in Huntsville.

VHDL Discussion Subprograms

IAS 0600 Digital Systems Design

ECE 434 Advanced Digital System L11

VHDL Data Types Module F3.1.

EEL4712 Digital Design (VHDL Tutorial).

Presentation transcript:

CPE 528: Lecture #4 Department of Electrical and Computer Engineering University of Alabama in Huntsville

Functions and Procedures Operator Overloading Outline VHDL operators Functions and Procedures Operator Overloading Multivalued Logic and Signal Resolution IEEE 1164 Standard Logic Generics Generate Statements 02/12/2018 UAH-CPE528

VHDL Operators Binary logical operators: and or nand nor xor xnor Relational: = /= < <= > >= Shift: sll srl sla sra rol ror Adding: + - & (concatenation) Unary sign: + - Multiplying: * / mod rem Miscellaneous: not abs ** Class 7 has the highest precedence (applied first), followed by class 6, then class 5, etc 02/12/2018 UAH-CPE528

Example of VHDL Operators 02/12/2018 UAH-CPE528

Example of Shift Operators 02/12/2018 UAH-CPE528

VHDL Functions Functions execute a sequential algorithm and return a single value to calling program A = “10010101” General form 02/12/2018 UAH-CPE528

For Loops 02/12/2018 UAH-CPE528

Add Function 02/12/2018 UAH-CPE528

VHDL Procedures Facilitate decomposition of VHDL code into modules Procedures can return any number of values using output parameters General form procedure procedure_name (formal-parameter-list) is [declarations] begin Sequential-statements end procedure_name; procedure_name (actual-parameter-list); 02/12/2018 UAH-CPE528

Procedure for Adding Bit_vectors 02/12/2018 UAH-CPE528

Parameters for Subprogram Calls 02/12/2018 UAH-CPE528

Review: Operator Overloading Operators +, - operate on integers Write procedures for bit vector addition/subtraction addvec, subvec Operator overloading allows using + operator to implicitly call an appropriate addition function How does it work? When compiler encounters a function declaration in which the function name is an operator enclosed in double quotes, the compiler treats the function as an operator overloading (“+”) when a “+” operator is encountered, the compiler automatically checks the types of operands and calls appropriate functions 02/12/2018 UAH-CPE528

VHDL Package with Overloaded Operators 02/12/2018 UAH-CPE528

Multivalued Logic Bit (0, 1) Tristate buffers and buses => high impedance state ‘Z’ Unknown state ‘X’ e. g., a gate is driven by ‘Z’, output is unknown a signal is simultaneously driven by ‘0’ and ‘1’ 02/12/2018 UAH-CPE528

Tristate Buffers Resolution function to determine the actual value of f since it is driven from two different sources 02/12/2018 UAH-CPE528

VHDL signals may either be resolved or unresolved Signal Resolution VHDL signals may either be resolved or unresolved Resolved signals have an associated resolution function Bit type is unresolved – there is no resolution function if you drive a bit signal to two different values in two concurrent statements, the compiler will generate an error 02/12/2018 UAH-CPE528

Signal Resolution (cont’d) signal R : X01Z := ‘Z’; ... R <= transport ‘0’ after 2 ns, ‘Z’ after 6 ns; R <= transport ‘1’ after 4 ns; R <= transport ‘1’ after 8 ns, ‘0’ after 10 ns; 02/12/2018 UAH-CPE528

Resolution Function for X01Z Define AND and OR for 4-valued inputs? 02/12/2018 UAH-CPE528

AND and OR Functions Using X01Z ‘0’ ‘1’ ‘Z’ OR ‘X’ ‘0’ ‘1’ ‘Z’ 02/12/2018 UAH-CPE528

IEEE 1164 Standard Logic 9-valued logic system ‘U’ – Uninitialized ‘X’ – Forcing Unknown ‘0’ – Forcing 0 ‘1’ – Forcing 1 ‘Z’ – High impedance ‘W’ – Weak unknown ‘L’ – Weak 0 ‘H’ – Weak 1 ‘-’ – Don’t care If forcing and weak signal are tied together, the forcing signal dominates. Useful in modeling the internal operation of certain types of ICs. 02/12/2018 UAH-CPE528

Resolution Function for IEEE 9-valued 02/12/2018 UAH-CPE528

AND Table for IEEE 9-valued 02/12/2018 UAH-CPE528

AND Function for std_logic_vectors 02/12/2018 UAH-CPE528

Example: rise/fall time modeling Generics Used to specify parameters for a component in such a way that the parameter values must be specified when the component is instantiated Example: rise/fall time modeling 02/12/2018 UAH-CPE528

Rise/Fall Time Modeling Using Generics 02/12/2018 UAH-CPE528

Generate Statements Provides an easy way of instantiating components when we have an iterative array of identical components Example: 4-bit RCA 02/12/2018 UAH-CPE528

4-bit Adder 02/12/2018 UAH-CPE528

4-bit Adder using Generate 02/12/2018 UAH-CPE528