Trigger system Marián Krivda (University of Birmingham) on behalf of the NA62 Collaboration 20-26/5/2012 Pisa meeting

Content Physics motivation Requirements Triggering detectors Overall triggering system and infrastructure Current L0 processor development and synchronization card Local trigger Unit (LTU) Software for LTU Setup for dry and technical run Summary 20-26/5/2012 Pisa meeting

Dictionary L0TP – L0 Trigger Processor TTC - Timing, trigger and control LTU – Local trigger unit TTCex – TTC encoder/transmitter module TTCit – Interface Test board TTCoc – optical coupler (fan out of optical signals) 20-26/5/2012 Pisa meeting

Physics motivations Ultra rare K decay in flight -> pi+ nu nubar GOAL: 100 events (~10% bkg) in 2 years data-taking Standard Model Branching Ratio is 8 x 10(-11) and therefore the majority of kaon decays are background Beam rate is ~800 MHz, Kaon rate is 50 MHz and about 20% of kaons decay in the vacuum region 20-26/5/2012 Pisa meeting

NA62 detector layout CHANTI CHOD NA62 uses 40 MHz clock but the beam is from SPS and so it has a time structure totally different from LHC (4.8 sec flat top out of 13 sec) Kaons are distributed asynchronously at the flat top 20-26/5/2012 Pisa meeting

Requirements Integrated, fully digital trigger with 3 levels Hardware L0, software L1/L2 Trigger rate 1 MHz at L0 level High trigger efficiency, deadtimeless Low probability of random veto Readout without zero suppression of candidate events Flexibility, configurability Simple, controllable trigger cuts Low jitter system (GTK has 100 ps resolution) 20-26/5/2012 Pisa meeting

Main triggering detectors CHOD 20-26/5/2012 Pisa meeting

L0 trigger system and distribution L0 processor 40 MHz clock source Trigger inputs BUSY/ ERROR Clock + Triggers TTC partition LTU + TTCex LTU + TTCex LTU + TTCex LTU + TTCex . . . . . . . . . . . . . . . . . . . . . . . TTCrx TTCrx TTCrx TTCrx . . . . . . . . . . . . . . . . . . . . . . . QPLL QPLL QPLL QPLL FEE FEE FEE FEE For jitter < 50 ps RMS QPLL will be used 20-26/5/2012 Pisa meeting

L0 Trigger Processor (L0TP) Tasks: merge “time of interest/veto” lists re-synchronize L0 trigger to drive TTC provide trigger data for readout R&D is going on to validate the possibility of having L0TP on a PC (Ferrara) Synchronization card 20-26/5/2012 Pisa meeting

LTU + TTCex + TTCoc + TTCit 6U VME cards 1 LTU+TTCex per detector Optical transmission of A and B channel TTCex Local Trigger Unit LTU (Alice) Monitoring of TTC TTCit TTCoc 1:32 Trig. data from LOTP LVDS (7) Burst Warning ejection (WE) Detector CHOKE/ERROR 31 optical outputs to FEE ser. data channel A ser. data channel B clock clock 40 MHz clock source 20-26/5/2012 Pisa meeting

LTU Global mode Local mode Receive triggers from L0 processor Emulate L0 processor - triggers (start signal can be: BC downscale, random, Pulser input) Serialize trigger data for TTC ch.B Encode triggers and send them to TTC Receive CHOKE/ERROR from detector and propagate it to L0 processor Snapshot memory – 27 ms 20-26/5/2012 Pisa meeting

NA62 LTU FPGA LTU FPGA Front panel L0TP emulator L0 L0_data [5:0] BC RND SOFT L0 select MUX L0 Delay A L0_data [5:0] L0data select 6 L0 FIFO TTCvi MUX Delay B clock Delay lines PLL in_bc Toggle SEL BC_ff L0_data[3] ADC R C adc_in LTU FPGA ADC ser. data TTC - B TTC - A 20-26/5/2012 Pisa meeting

LTU I/O 16-pin connector 7 LVDS links Clock input – ECL signal 1 NIM input 2 ECL input 2 LVTTL outputs 2 ECL outputs 1 NIM output 2 LVDS inputs 2 LVDS outputs Clock input – ECL signal Pulser input – ECL input Burst input - NIM input Warning injection – LVDS input Scope probe outputs – 2 LVTTL outputs Ser. data ch.A and B - 2 ECL outputs BUSY/ERROR – LVDS input BUSY for L0 processor – LVDS output 20-26/5/2012 Pisa meeting

TTC requirements Distribute a clock 40 MHz Jitter < 50 ps RMS - triggers (6 bits for each trigger) - start of burst - end of burst - event counter at the end of burst - warning ejection signals 20-26/5/2012 Pisa meeting

TTC network (Birmingham) 20-26/5/2012 Pisa meeting

TTC channel B format 16 bits at 40MHz, max. rate 2,5 MHz (8 data bits) If 14b TTCrx ADDR == 0 => also Broadcast command/data 20-26/5/2012 Pisa meeting

TTC format for NA62 A channel - L0 trigger: synch. signal (25ns pulse if ‘L0 accept’) B channel L0 trigger type: asynch. message – short broadcast (6-bits info related to 25 ns pulse), Event counter at the end of burst Start of burst, end of burst, warning ejection (a few µs before spill) – short broadcast message (priority message - guaranteed time precision by inhibit interval) 20-26/5/2012 Pisa meeting

Software for LTU NA62 (Bratislava) LTU software for Configuration and Control Monitoring L0 processor emulation 2 types of LTU software LTU direct LTU DIM architecture 20-26/5/2012 Pisa meeting 9/12/2009 18

LTU direct software 20-26/5/2012 Pisa meeting 9/12/2009 19

LTU Software: DIM architecture 20-26/5/2012 Pisa meeting

TTCit board - independent monitoring of TTC traffic Receives data from TTCrq (TTCrx + QPLL) Decoding of data Display triggers and possible trigger errors on the front panel Read snapshot memory via VME bus 2 LVTTL outputs for scope 1 LVDS input 20-26/5/2012 Pisa meeting

Software for TTCit board (Bratislava) B-channel short broadcast test Data bits 8 bit data data[0] and data[1] have special meaning effectively only data[7:2] can be used for the message Hamming bits Test: data messages set by LTU software LTU-->TTCex --> TTCit Strobed data 20-26/5/2012 Pisa meeting

Event ID and synchronization Event ID is defined by: Time stamp : # counts of BC (40.078 MHz) from start of burst ‐ BC stamp Fine time: FEE runs BC and also clock 40Mhz/256 Trigger input signals are asynchronous messages (send over gigabit Ethernet). They contain timestamp (BC) of event which produced trigger. L0TP runs BC, receives messages, decode them and if condition fulfilled L0TP sends readout trigger over TTC (triggers are send synch., trigger message is sent asynch.) FEE receives trigger and reads events corresponding to the all BC period (25ns) or more. Synchronization Sync. Trigger -> synch. Event ID counters L0TP – LTU clock phase adjustment LTU – TTCex clock phase adjustment 20-26/5/2012 Pisa meeting

Setup for dry and technical run TALK board (LOTP replacement by CERN) LTUs (Birmingham) + TTCex (CERN) 20-26/5/2012 Pisa meeting

Summary NA62 trigger system - up to date design using of LHC experiences Implementation in progress: TTC network ready LTU and TTC ready for standalone testing of detector FEE L0 processor in progress Dry and technical run 2012 – first test of integration Trigger/DAQ/Detector 20-26/5/2012 Pisa meeting

Back up slides 20-26/5/2012 Pisa meeting

What do we need in the lab ? Precise clock generator (40.078 MHz) 6U VME crate VME processor LTU module TTCex module 20 dB attenuator/TTCoc Lemo cables Single mode optical fibers Appropriate software 20-26/5/2012 Pisa meeting

TTCex ECL input for external clock ECL inputs for TTC channel A and channel B 10 optical outputs Incorporates encoders driven by an internal VCXO/PLL with very low jitter and can deliver the optimum optical signal level (-19 dBm) through 1:32 tree couplers to 320 destinations 20-26/5/2012 Pisa meeting