Instructor: Prof. Chung-Kuan Cheng CSE246 Adder – Part II Instructor: Prof. Chung-Kuan Cheng

Zimmerman’s Heuristic Approach Problem formulation Given depth constraint, generate a parallel prefix adder of minimum size Two step Heuristic Start with a serial prefix adder Compress to a fastest prefix structure at the cost of increasing size LSB to MSB, low level to high level Expand to reduce size, subject to depth constraint MSB to LSB, high level to low level 2018/12/2

Zimmerman’s Heuristic Approach Local compression/expansion operation Up/down shift The compression oper 2018/12/2

Zimmerman’s Heuristic Approach Advantages Simple and fast Product depth-size optimal result in many cases Handles non-uniform input arrival times Disadvantage No guarantee on optimality 2018/12/2

Prefix Adder with arbitrary input arrival time profile Non-uniform input arrival times represented in real number How to construct the fastest prefix adder under arbitrary input arrival time profile? 2018/12/2

Cont’ Timing model t[i:j] = max{t[i:k] , t[k-1:j] }+C All (G,P) generators have the same delay C Denote the output timing of generator (G,P)[i:j] as t[i:j] Suppose in the prefix graph, (G,P)[i:j] is generated from (G,P)[j:k] and (G,P)[k-1:j], then t[i:j] = max{t[i:k] , t[k-1:j] }+C 2018/12/2

Dynamic Programming – The idea Image a full array of partial prefix results All (G,P) signals of length i are on level i Rightmost signals are wanted prefix results Generate all the (G,P) signals row by row, from lower level to higher level For each (G,P) signal, find the scheme that leads to best timing, i.e., find the partition point k such that (G,P)[i:j] = (G,P)[i:k] (G,P)[k-1:j] t[i:j] = min{max{t[i:k] , t[k-1:j] }+C} t[n:n] t[n-1:n-1] t[2:2] t[1:1] Level 1: Level 2: Level n: … . k t[n:n-1] t[2:1] t[n:n-2] t[3:1] t[n:2] t[n-1:1] t[n:1] 2018/12/2

Dynamic Programming A 5-bit example 2(g4p4) 4(g3p3) 3(g2p2) 1(g1p1) Level 1 8 7(GP[3,0]) Level 4 8 7 5(GP[2,0]) Level 3 6 5 3(GP[1,0]) Level 2 7 8 8(GP[4,0]) Level 5 2018/12/2

Dynamic Programming Complexity Hints for reducing complexity For (G,P)[i:j], search (i-j) combinations Overall O(n3) Hints for reducing complexity For (G,P)[i:j], there might more than one optimal partition points, but we want just one At least one optimal partition point of (G,P)[i:j] is bounded by the optimal partition points of (G,P)[i-1:j] and (G,P)[i:j+1] 2018/12/2

Backward Reduction I Some of the partial prefix results are not used, hence can be removed Level 1 Level 2 Level 3 Level 4 Level 5 (a) (b) 2018/12/2

Backward Reduction II Some nodes may be over tightened, and can be relaxed to reduce area 3(g4p4) 6(g3p3) 7(g2p2) 11(g1p1) 13 (G,P)[2,1] 9 8 10 (G,P)[3,1] (G,P)[4,1] (G,P)[4,2] (13) 3(g4p4) 6(g3p3) 7(g2p2) 11(g1p1) 13 (G,P)[2,1] (G,P)[3,1] (G,P)[4,1] (G,P)[4,2] 11 (11) 8 () 9 (9) 10 (11) 8 (9) 9 11 (11) 9 (9) (13) (11) (9) 2018/12/2

A missing detail (G,P) signals allows overlap  search space increases However, allowing overlapping does not produce better timing (G,P)[i:j] = (G,P)[i:k] (G,P)[l:j] l ≥k 2018/12/2

Function level optimization Carry Skip Adder A0 a3,0 b3,0 cin c4 1 p3,0 A1 a7,4 b7,4 c8 p7,4 A2 a11,8 b11,8 c12 p11,8 x If p3,0=p3p2p1p0 = 1, then x = cin 2018/12/2

False Path A1 <- MUX <- A0 <- cin is a false path If carry is from cin, then block must have p3p2p1p0 = 1 Since p3,0 = 1, g3,0 must be 0 The carry is not generated from A0 The carry needs not to propagate via A0, it will go from the MUX 2018/12/2

False Path: Cycles A3,0 B3,0 Cout Cin Adder S3,0 Cycles of False Paths: Eg. 1’s complement number addition Positive: x Negative: (2n-1)-x Addition (2n-1)-x + (2n-1)-y = 2n+(2n-1)-(x+y)-1 A3,0 B3,0 Cout Cin Adder S3,0 2018/12/2

Example -3-5 = -8 11100 -3 + 11010 -5 110110 110111 -8 0+0=0 11111 0 + 11111 0 111110 111111 0 2018/12/2

Multi-Operand Addition Carry save adder: a (3,2) counter 2018/12/2

Example A (3,2) counter compresses X rows to 2/3X rows each time Tree structure in implementation 2018/12/2

Other Counters (7,3) counter (5,3) counter Ca Cb S0 S2 S1 S0 Design of (5,3) counter using full adders Ca Cb S0 2018/12/2