Commodity Flash ADC-FPGA Based Electronics for an Nestor Institute for Astroparticle Physics Commodity Flash ADC-FPGA Based Electronics for an Underwater Neutrino Telescope Theodoros Athanasopoulos Nestor - NOA VLVnT-08 23/04/2008 Toulon / France 1/12

Market Search Requirements. System Functional Description. Nestor Institute for Astroparticle Physics Outline Market Search Requirements. System Functional Description. Clock distribution Electronics. Readout Electronics. Detector Monitor & Control Electronics. Calibration / Verification of Electronics. VLVnT-08 23/04/2008 Toulon / France 2/12

Sampling Rate >200MS/s/CH Analog Input Bandwidth ≥ 200MHz Nestor Institute for Astroparticle Physics Market Search Requirements Waveform Capture for acquiring the information from the PMT signals (Time-Amplitude) Sampling Rate >200MS/s/CH Analog Input Bandwidth ≥ 200MHz -50mV≤Analog Input Signal Range≥-1.2V (20SPEs) Amplitude resolution ≥ 8-bit External I/Os for signaling Standard-High bandwidth interfaces VLVnT-08 23/04/2008 Toulon / France 3/12

Detector System Block Diagram Nestor Institute for Astroparticle Physics Detector System Block Diagram Shore Station Storage GPS Clock Encoding and Transmission Command Tx Data Rx Software Module Gbit Ethernet Gbit Ethernet card with Optical SFP Optical DEMUX Optical MUX On Shore Off Shore 50km of fiber Readout Electronics Readout Host Optical MUX Optical DEMUX Clock Reception Synthesis & Fan-out Detector Monitor & Control Electronics Gbit Ethernet card with Optical SFP VLVnT-08 23/04/2008 Toulon / France 4/12

Detector Clock Distribution System Nestor Institute for Astroparticle Physics Detector Clock Distribution System GPS Disciplined Rubidium Clock Synchronized to UTC Time Clock Buffering and Fan-out into 4 channels (Max Skew 35ps) Electrical to Optical Conversion and transmission of a 10MHz clock trough fiber 250MHz Clock to Readout Electronics 50km of fiber Mother Card FPGA Virtex 2 Pro Virtex-4 QUAD FADC Optical to Electrical Conversion and regeneration of the10MHz clock. Synthesis of 250MHz clock locked to the 10MHz Reference VLVnT-08 23/04/2008 Toulon / France 5/12

Detector Monitor and Control Nestor Institute for Astroparticle Physics Detector Readout Electronics The FPGA Computing Company Glasgow Scotland 250MHz Clock Continuous Sampling at 250MS/s/ch Without a Trigger. Trigger Decision Every 4ns No Dead Time Between Triggers PMT 1 PMT 2 PMT 3 PMT 4 PMT 5 PMT 6 PMT 7 PMT 8 PMT 9 PMT 10 PMT 11 PMT 12 Detector Monitor and Control External I/O bank which can be used for external trigger / calibration signals Mother Card Xilinx FPGA Virtex 2 Pro Virtex-4 QUAD FADC 122 bit bus 64 bit bus Slot card 2 Slot card 1 Slot card 0 Ext I/O 64bit PCI / PCI-X Interface to Readout Host FADC MAX1215 (12-bit) BS1 VLVnT-08 23/04/2008 Toulon / France 6/12

To and from Readout Electronics TTL I/O for activating and Nestor Institute for Astroparticle Physics Detector Monitor & Control Electronics Calibration LED Beacon 1 FPGA Controls all the different devices of the Detector Monitor and Control Electronics (ADCs/DACs/RELAYS/Calibration LED Beacons) and is directly connected to the Readout Electronics board. Detector Monitor & Control Electronics ADCs for environmental sensor readout and for HV monitoring ALTERA FLEX10K FPGA DACs for controlling PMT HV To and from Readout Electronics TTL I/O for activating and controlling peripheral devices Calibration LED Beacon 2 VLVnT-08 23/04/2008 Toulon / France 7/12

Calibration Pulse Amplitude Control Detector Monitor and Control Nestor Institute for Astroparticle Physics Calibration of Detector Readout Electronics Custom Card Allows for multiplexing PMT inputs with calibration pulse inputs PMT 1 PMT 2 PMT 3 PMT 4 PMT 5 PMT 6 PMT 7 PMT 8 PMT 9 PMT 10 PMT 11 PMT 12 Isolation transformers Calibration Pulse Calibration Pulse Amplitude Control 250MHz CLK Detector Monitor and Control Mother Card FPGA Virtex 2 Pro Virtex-4 Slot card 2 Slot card 1 Slot card 0 QUAD FADC QUAD FADC QUAD FADC FPGA Virtex 2 Pro FPGA Virtex-4 FPGA Virtex-4 FPGA Virtex-4 Ext I/O VLVnT-08 23/04/2008 Toulon / France 8/12

Readout Electronics Consumption (W) Readout Host (W) Nestor Institute for Astroparticle Physics Power Consumption The whole system is powered through DC-DC converters from a 300V supply line. Configuration Readout Electronics Consumption (W) Readout Host (W) Monitor & Control Electronics Total System Consumption Idle 10 60 8 78 12 Channels 120 90 210 VLVnT-08 23/04/2008 Toulon / France 9/12

Test Data (Pulse Height) Nestor Institute for Astroparticle Physics Test Data (Pulse Height) Test data taken at the Nestor dark room test bed with PMTs at various settings and voltages. Gaps amongst histogram bins are an artifact of the display software VLVnT-08 23/04/2008 Toulon / France 10/12

Positive Experience with FADC-FPGA Readout Electronics in our test bed Nestor Institute for Astroparticle Physics Conclusion Positive Experience with FADC-FPGA Readout Electronics in our test bed 12 channels at 250MSPS each. Local processing power for algorithm implementations External I/O bank for signaling with other electronics Integration of the Readout electronics to custom and legacy electronics as we have done. Ability to remotely parameterize the electronics operation Next Steps Long Term Stability Test with convection cooling Working on high throughput interconnect to shore “ALL DATA TO SHORE” BenNUEY (Mother Card) BenADC (Daughter Cards) VLVnT-08 23/04/2008 Toulon / France 11/12

Programmable Algorithm Parameters Feature Min value Max value Nestor Institute for Astroparticle Physics Programmable Algorithm Parameters Feature Min value Max value Input Signal Threshold Entire Input Signal Range(1.45Vp-p *attenuation factor) Coincidence Window 60ns 200ns Majority 12 Total Event Size 20ns 4μs Pro – Event Recording Size 12ns 800ns All the programmable parameters can be altered via software remotely VLVnT-08 22/04/2008 Toulon / France 12/12