Semiconductor Memories

Outline Concept/need of memory Parameters Types/classification Basic features Basic Cell circuits Peripheral circuitry

Concept Data storage essential for processing Binary storage Switches How do you implement this in Hardware?

Requirements Easy reading Easy Writing High density Speed, more speed and still more speed

Memory Chip Configuration

Semiconductor Memory Classification Non-Volatile Read-Write Memory Read-Write Memory Read-Only Memory Random Non-Random EPROM Mask-Programmed Access Access 2 E PROM Programmable (PROM) SRAM FIFO FLASH LIFO DRAM Shift Register CAM

RAM Random write and read operation for any cell Volatile data Most of computer memory DRAM Low Cost High Density Medium Speed SRAM High Speed Ease of use Medium Cost

ROM Non-volatile Data Method of Data Writing Mask ROM PROM Data written during chip fabrication PROM Fuse ROM: Non-rewritable EPROM: Erase data by UV rays EEPROM: Erase and write through electrical means Speed 2-3 times slower than RAM Upper limit on write operations Flash Memory – High density, Low Cost

Basic Cells SRAM DRAM

Static CAM Memory Cell ••• ••• CAM Bit Word ••• Wired-NOR Match Line int S ••• •••

CAM in Cache Memory Hit Logic Address Decoder CAM SRAM ARRAY ARRAY Input Drivers Sense Amps / Input Drivers Address Tag Hit R/W Data

ROM EEPROM Fuse ROM Floating Gate

MOS NAND ROM V DD Pull-up devices BL [0] BL [1] BL [2] BL [3] WL [0] WL [1] WL [2] WL [3] All word lines high by default with exception of selected row

Non-Volatile Memories The Floating-gate transistor (FAMOS) D Source Drain t ox t ox n + p n +_ Substrate Schematic symbol Device cross-section

Floating-Gate Transistor Programming 20 V 10 V 5 V D S Avalanche injection 0 V - 5 V D S Removing programming voltage leaves charge trapped 5 V - 2.5 V D S Programming results in higher V T .

A “Programmable-Threshold” Transistor

Periphery Decoders Sense Amplifiers Input/Output Buffers Control / Timing Circuitry

Row Decoders Collection of 2M complex logic gates Organized in regular and dense fashion (N)AND Decoder NOR Decoder

Hierarchical Decoders Multi-stage implementation improves performance • • • WL 1 WL A A A A A A A A A A A A A A A A 1 1 1 1 2 3 2 3 2 3 2 3 • • • NAND decoder using 2-input pre-decoders A A A A A A A A 1 1 3 2 2 3

Sense Amplifiers Idea: Use Sense Amplifer small s.a. transition input C D V × I av ---------------- = make V as small as possible small large Idea: Use Sense Amplifer small transition s.a. input output

Sense Amp Operation D V (1) (0) t Sense amp activated PRE BL Sense amp activated Word line activated

Differential Sense Amplifier V DD M M 3 4 y Out bit M M bit 1 2 SE M 5 Directly applicable to SRAMs

Reliability and Yield