Digital Logic & Design Dr. Waseem Ikram Lecture 40

Memory array decoded by Row and Columns Decoders

Input/Output Data Circuit

Timing diagram of a Read Cycle

Timing diagram of a Write Cycle

Block diagram of a Synchronous Burst RAM

Burst Logic Circuit

Writing a 1 or 0 into the DRAM cell

Reading a 0 or 1 from the DRAM cell

Refreshing a DRAM cell

Circuit Diagram of a 1M x 1 DRAM Memory Array 1024 rows x 1024 columns Input/Output Buffers and Sense Amplifiers Refresh Counter Control Timing Row Decoder Column Data Selector Address Latch D OUT IN W / R E RAS CAS Lines A -A 9

Recap Memory Latches and Flip-flops (small memory) Computer Program Memory (large memory) Data Storage Bits, Nibbles, Bytes, Words Memory Storage Storage array of cells (stores 0 or 1) Two dimensional array row & column

Recap Memory Organization Byte, Nibble, Bit Memory Capacity and Density Memory Block diagram and Signals Address, Data, R/W and CS

Recap Static RAM cell implementation Internal structure of 8 x 4 RAM 16K x 8 RAM chip

Memory Row and column decoders in RAM (fig 1) Input/Output RAM circuit (fig 2) Read Cycle (fig 3) Write Cycle (fig 4)

Sync. Burst SRAM & DRAM Sync. Burst SRAM (fig 5) Flow through SRAM Pipelined SRAM Burst Logic Circuitry (fig 6) DRAM Structure (fig 7a) Writing to DRAM (fig 7a) Reading from DRAM (fig 7b) Refreshing DRAM (fig 7c) Address Multiplexing (fig 8)