CMOS Combinational Gate 2-Dec-18 EE 4271 VLSI Design CMOS Combinational Gate

CMOS Combinational Circuits 2-Dec-18 CMOS Combinational Circuits Implementation of logic gates and other structures using CMOS technology. Basic element: transistor 2 types of transistors: n-channel (nMOS) and p-channel (pMOS) Type depends on the semiconductor materials used to implement the transistor. We want to model transistor behavior at the logic level in order to study the behavior of CMOS circuits  view pMOS and nMOS transistors as swithes. 2-Dec-18 Combinational Logic

CMOS transistors as Switches 2-Dec-18 CMOS transistors as Switches 3 terminals in CMOS transistors: G: Gate D: Drain S: Source nMOS transistor/switch X=1 switch closes (ON) X=0 switch opens (OFF) pMOS transistor/switch X=1 switch opens (OFF) X=0 switch closes (ON) 2-Dec-18 Combinational Logic

2-Dec-18 Networks of Switches Use switches to create networks that represent CMOS logic circuits. To implement a function F, create a network s.t. there is a path through the network whenever F=1 and no path when F=0. Two basic structures: Transistors in Series Transistors in Parallel 2-Dec-18 Combinational Logic

Transistors in Series/Parallel 2-Dec-18 Transistors in Series/Parallel nMOS in Series nMOS in Parallel a a Path between points a and b exists if both X and Y are 1  X•Y a a Path between points a and b exists if either X or Y are 1  X+Y X X:X X Y X:X Y:Y Y Y:Y b b b b pMOS in Parallel pMOS in Series a a a a Path between points a and b exists if either X or Y are 0  X’+Y’ Path between points a and b exists if both X and Y are 0  X’•Y’ X X:X’ X Y X:X Y:Y Y Y:Y’ b b b b 2-Dec-18 Combinational Logic

Networks of Switches (cont.) 2-Dec-18 Networks of Switches (cont.) In general: nMOS in series is used to implement AND logic pMOS in series is used to implement NOR logic nMOS in parallel is used to implement OR logic pMOS in parallel is used to implement NAND logic Observe that: 1 is the complement of 4, and vice-versa 2 is the complement of 3, and vice-versa 2-Dec-18 Combinational Logic

CMOS Inverter Operation: 2-Dec-18 CMOS Inverter X F = X’ +V GRD F = X’ X Logic symbol Transistor-level schematic Operation: X=1  nMOS switch conducts (pMOS is open) and draws from GRD  F=0 X=0  pMOS switch conducts (nMOST is open) and draws from +V  F=1 2-Dec-18 Combinational Logic

Fully Complementary CMOS Networks Basic Gates 2-Dec-18 Fully Complementary CMOS Networks Basic Gates 2-Dec-18 Combinational Logic

Fully Complementary CMOS Complex Gates 2-Dec-18 Fully Complementary CMOS Complex Gates Given a function F: First take the complement of F to form F’ Implement F’ as an nMOS net and connect it to GRD (pull-down net) and F. Find dual of F’, implement it as a pMOS net and connect it to +V (pull-up net) and F. Connect switch inputs. 2-Dec-18 Combinational Logic

Fully Complementary CMOS Networks Complex Gates - Example 2-Dec-18 Fully Complementary CMOS Networks Complex Gates - Example F = (A+B)(A+C’) F’ = A’B’+A’C=A’(B’+C) 2-Dec-18 Combinational Logic

CMOS Transmission Gate (TG) 2-Dec-18 CMOS Transmission Gate (TG) 2-Dec-18 Combinational Logic

2-input MUX Using CMOS TGs 2-Dec-18 2-input MUX Using CMOS TGs 2-Dec-18 Combinational Logic