Fanout Clock Skew Lab Exercise Jared Coltharp

Basic concept Why? Main consideration What is “good” skew? IC output driver limitations Main consideration Output-output skew Latency What is “good” skew? Could either be absolute time or clock cycle percentage

Schematic Considerations Components HSD Rules Each IC has 6 gates Only 15 gates needed, 3 are unused Unused inputs must be pulled up or down Which gates to use? Not needed, rise time is only 6 ns l/4 is about 8 inches Longest single trace is 6.5 in, next is 5 in No terminations, few decoupling capacitors

Board Considerations Traces routed without consideration for timing Routing Placement Traces routed without consideration for timing Unfortunately, vias Plan to test at TPs and at chip pins Significant Difference ICs placed purposefully far apart Capacitors placed right next to Vcc pin Test points placed for schematic convenience

Ideal Trace Length and Delay (Excluding Gates) Propagation Delay Ideal Trace Length and Delay (Excluding Gates) Path Length with TP Delay with TP Length without TP Delay without TP O1 6682.51 1240.432154 4286.8 795.7316272 O2 11836.77 2197.184906 8395.35 1558.375832 O3 9646.41 1790.602203 8179.99 1518.399914 O4 11692.12 2170.334439 9496.41 1762.75865 O5 10423.84 1934.911628 9128.13 1694.397158 O6 8303.13 1541.257615 6241 1158.477439 O7 6375.93 1183.523643 3832.74 711.4473353 O8 8551.1 1587.286721 1956.13 363.1040655 There will clearly be a large difference due to propagation times, especially going from using the test points to not using the test points.

Outline for Lab Exercise First, construct the board once it is fabricated Test propagation delay for each clock signal with reference to the function generator clock Pick the quickest clock signal (should be O1 or O7) and measure skew with other clock signals Measure difference between each clock signal’s test point and IC pin Determine the maximum output skew for each case Report guidelines

Steps to Ensure Smooth Lab Conduction Perform the lab exercise Determine what changes could be made to the board to make conduction easier Ground pins near the ICs needed? Is timing actually visible? What effect does the propagation delay through the IC have on skew? May need to make a second revision of the board