SVT detector electronics Mauro Villa INFN & Università di Bologna Overview: - SuperB SVT open options - F.E. chips - Trigger handling

Detectors: Layer0 Outer Layers Plan Striplets baseline option for TDR: Better physics performance (lower material ~0.5% vs 1% hybrid pixel, MAPS or thin hybrid pixel in between but not yet mature!) Upgrade to pixel (Hybrid or CMOS MAPS), more robust against background, foreseen for a second generation of Layer0 SVT Mechanics will be designed to allow a quick access/removal of Layer0 Outer Layers Will be most probably strip detectors (up to 37 cm long) Evaluation of FSSR2 chip as a possible candidate for the readout of short (Layer0) and long (outer layers) strips 2 Frascati, 28/09/10

FSSR2 FSSR2, designed for the BTeV Forward Silicon Tracker : Fast, data driven readout architecture, with no analog storage, with large output bandwidth Mixed-signal integrated circuit for the readout of silicon strip detectors (selectable shaper peaking time: 65-85-100-125 ns) TSMC 0.25 µm CMOS tech. with enclosed NMOS  Rad. Hard 128 analog channels, sparsified digital output with address, timestamp, and pulse height information for all hits Architecture designed to run with 132 ns bunch crossing (timestamp granularity = BCO clock = 7.6 MHz nominal), readout clock @ 70 MHz 840 Mb/s output data rate V. Re Frascati, 28/09/10 3 3

Signal/Noise ratios FSSR2 as is Worst case: SVT external layers, Phi-side layer5. Strips 37 cm long. C = 1.5 pF/cm R = 10 W/cm CD = 55 pF, RS = 370 W FSSR2 noise vs det Capacitance Layer0 CD = 9pF FSSR2 as is Signal = 24000 e- (Si 300 um thick) Increasing peaking time: S/N = 11 at tP = 0.12 ms S/N = 20 at tP = 0.4 ms S/N = 26 at tP = 1 ms

Occupancy expected on L0-L1 In Layer 1 we can expect a FSSR2 event rate up to about 500 kHz on each strip: Assuming bkg rate of 1MHz/cm2, 2 hit/track, 10.7cm strip length, 50μm pitch, including a safety factor 5 Event Rate = 535 kHz  > 3 MHz in Layer 0 (assuming bkg 200 MHz/cm2) At 30 MHz FSSR clock, the average occupancy in an FSSR clock period is 1.8% (with a factor of 5 safety factor)  > 10 % in Layer 0 Will the FSSR2 chip be efficient in these tough conditions? Frascati, 28/09/10 5 5

Verilog studies on background MC Best performance configuration: Parameter Value # Active Output 6 Lines FSSR Clock (BCO) 30 MHz Master Clock 80 MHz Threshold rate (best conditions): 312 kHz Frascati, 28/09/10 6

FSSR2 redesign Chip redesign needed in few areas: - analog for the high capacitance, long peaking time and correct handling of n-side strips, - digital to cope with the high rate 128 channels of analog circuits Ongoing discussions between Pisa, Pavia, Bergamo, Trieste Fermilab End-Of-Set Logic 16 Sets of logic each handling 8 analog channels CORE Core Logic PROGRAMMABLE REGISTERS Clock Control Logic Next Block Word Fermilab willing to upgrade the chip DACs DATA OUTPUT INTERFACE PROGRAMMING INTERFACE Word Serializer Steering Logic FSSR clk I/O MCA/MCB High Speed out Frascati, 28/09/10

FSSR3 and other readout chips SVT Front end chips will all be triggered. We’re about to abandon the SVT trigger capabilities at least at Level 1: - Not fast enough (long peaking time) - Too demanding for available chips - Too much bandwidth needed Striplet readout (FSSR3) will likely work in a triggerable only manner. Pixel options for L0 will be equipped with a dual function chip (triggerable/trigger source) but will be used as triggerable. Frascati, 28/09/10

DAQ reading chain for L0-L5 HDI +Transition card+FEB+ROM DAQ chain independent on the chosen FE options Optical 1 Gbit/s Optical Link 2.5 Gbit/s ~50 cm FEB ROM LV1 High rad area 10Mrad/year Off detector low rad area Counting room Std electronics SuperB Trigger is handled by the FEB and forwarded to HDI and/or chips. No direct SuperB trigger to chips. Frascati, 28/09/10 9

Trigger handling Close triggers Trigger SVT hit time information of 100-130 ns granularity. Close triggers Trigger TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 Event and hit time axis TS0 TS1 TS2 TS5 TS6 TS7 TS8 Event acquired (time axis) 150 kHz trigger, 6 us latency (better to foresee a margin for 12 us) and 70 ns minimum time separation are ok for SVT electronics. Frascati, 28/09/10 10 La Biodola, 1/06/10 10

Conclusions Strips readout chip FSSR2 to be redesigned Convergence towards a triggered SVT Better S/N ratios, higher efficiency @ high occupancy Lower requirements on bandwidths Contra: no trigger primitives; Savings Marginal saving in bandwidth on L2-L5 already dominated by physics rate rather than background 52 optical links (triggered) vs 56 O.L. (triggerable option) No SVT Trigger processors and associated links

SuperB SVT Layer 0 technology options Complexity Striplets option: mature technology, not so robust against background occupancy. Marginal with background rate higher than ~ 5 MHz/cm2 Moderate R&D needed on module interconnection/mechanics/FE chip (FSSR2 or new chip) Hybrid Pixel option: viable, although marginal. Reduction of total material needed! Reduction in the front-end pitch to 50x50 μm2 with data push readout (developed for DNW MAPS)  FE prototype chip (4k pixel, ST 130 nm) now under test. CMOS MAPS option: new & challenging technology. Sensor & readout in 50 μm thick chip! Extensive R&D (SLIM5-Collaboration) on Deep N-well devices 50x50μm2 with in-pixel sparsification. Fast readout architecture implemented CMOS MAPS (4k pixels) successfully tested with beams. Thin pixels with Vertical Integration: reduction of material and improved performance. Two options are being pursued (VIPIX-Collaboration) DNW MAPS with 2 tiers Hybrid Pixel: FE chip with 2 tiers + high resistivity sensor Sensor Digital tier Analog tier Wafer bonding & electrical interconn. 13 13 13

ENC equation thermal noise of preamplifier input NMOS thermal noise of the distributed resistance RS Parallel noise from detector leakage current and bias resistor 1/f noise of preamplifier input NMOS V. Re 14 14