Department of Electronic Engineering VLSI Technology Don-Gey Liu, Prof. Department of Electronic Engineering Feng Chia University 2018/12/3 FCUECE_DGL_VLSIT
Introduction Industries Development Fabrication Technology IC Families VLSI Technology 2003 2018/12/3 Introduction Industries Development Fabrication Technology IC Families Self-Aligned CMOS Process Flow Layout Design Roles of Computer Fabrication Equipment References 2018/12/3 FCUECE_DGL_VLSIT FCUECE_DGL_VLSIT
Industries 2018/12/3 FCUECE_DGL_VLSIT
Industries Jobs and Facilities 2018/12/3 FCUECE_DGL_VLSIT
Industries Technologies 2018/12/3 FCUECE_DGL_VLSIT
Development Integrated Circuits and profiles 2018/12/3 FCUECE_DGL_VLSIT
Development The 1st IC 2 Tx A few million Tx/Chip 2018/12/3 FCUECE_DGL_VLSIT
Development The trends 2018/12/3 FCUECE_DGL_VLSIT
Development The state-of-the-art technology 1 nm 2018/12/3 FCUECE_DGL_VLSIT
Development The 1st Transistor 2018/12/3 FCUECE_DGL_VLSIT
Development Grow junction transistor technology 2018/12/3 FCUECE_DGL_VLSIT
Development Alloy junction technology 2018/12/3 FCUECE_DGL_VLSIT
Development Double diffused mesa transistor technology Contact 1st diffusion Mesa etch 2nd diffusion 2018/12/3 FCUECE_DGL_VLSIT
Development Planar process by Jean Hoerni of Fairchild Photolithography 2018/12/3 FCUECE_DGL_VLSIT
Fabrication Technology Photolithography Process Repeated transferring patterns 底片 相紙 2018/12/3 FCUECE_DGL_VLSIT
Fabrication Technology Process Flow – To construct 3D structures by planar (2D) techniques 2018/12/3 FCUECE_DGL_VLSIT
Fabrication Technology Process Integration – Integrated planar thin-film technology Film deposition/growth PVD/CVD/Deposition Oxidation/Nitridation Impurity doping Photolithography Exposure/Development/Rinse Etching Wet etching/Dry etching 2018/12/3 FCUECE_DGL_VLSIT
Fabrication Technology Integration on substrates Isolation Metallization 2018/12/3 FCUECE_DGL_VLSIT
Fabrication Technology Modern CMOS IC SPTM(1P3M) M3 Via M2 P1 M1 2018/12/3 FCUECE_DGL_VLSIT
Fabrication Technology Modern COMS IC SPPM(1P5M) M5 M4 M3 Via2 M2 M1 Via1 P1 2018/12/3 FCUECE_DGL_VLSIT
Fabrication Technology Modern CMOS IC State-of-the-art Technology1 Cu technology 1 A. S. Brown, “Fast films [IC interconnect insulation], IEEE Spectrum , Vol. 40(2) , pp. 36 -40, Feb 2003. M1/P1 Channel M2 M3 M4 M5 M6 M7 M8 M9 2018/12/3 FCUECE_DGL_VLSIT
Fabrication Technology Cu Technology 1. Dielectrics formation Si Sub Underlying layers Spin-On / CVD Oxide 3. Etching Si Sub Underlying layers PR OX 4. Cu plating Si Sub Underlying layers PR OX 2. Photo-lithogrophy Si Sub Underlying layers PR Spin-On / CVD Oxide 5. Removal Si Sub Underlying layers OX Si Sub Underlying layers 2018/12/3 FCUECE_DGL_VLSIT
IC Families Bipolar IC 2018/12/3 FCUECE_DGL_VLSIT
IC Families NMOS IC 2018/12/3 FCUECE_DGL_VLSIT
IC Families CMOS IC 2018/12/3 FCUECE_DGL_VLSIT
Self-Aligned Process Flow LOCOS Chanstop VTH tuning 2018/12/3 FCUECE_DGL_VLSIT
Wafer in M1 PR Si3N4 SiO2 Substrate 2018/12/3 FCUECE_DGL_VLSIT
LOCOS isolation Active Area Bird’s beak Chanstop AA FOX B IMP 2018/12/3 FCUECE_DGL_VLSIT
Trench isolation Compact Active Area Dry etching CMP AA SiO2 CVD Oxidation 2018/12/3 FCUECE_DGL_VLSIT
Wells M3 M2 Phosphorus Implantation Boron Implantation 2018/12/3 FCUECE_DGL_VLSIT
Gate VTH tuning M5 M4 Arsenic Implantation Boron Implantation 2018/12/3 FCUECE_DGL_VLSIT
Gate M6 P1 2018/12/3 FCUECE_DGL_VLSIT
LDD extension SiO2 CVD Etch Back M8 M7 Boron Implantation Arsenic Implantation 2018/12/3 FCUECE_DGL_VLSIT
Source/Drain Electrodes M9 M10 Boron Implantation Arsenic Implantation 2018/12/3 FCUECE_DGL_VLSIT
Contact/M1 TiN removal Etch Back M11 SiO2 CVD CMP TiSi2/TiN Formation Ti Sputtering 2018/12/3 FCUECE_DGL_VLSIT
VIA1 M12 W CVD CMP Etching TiN Sputtering 2018/12/3 FCUECE_DGL_VLSIT
M2 M13 SiO2 CVD Plasma Etching 2018/12/3 FCUECE_DGL_VLSIT
VIA2 M12 CMP 2018/12/3 FCUECE_DGL_VLSIT
M2/Passivation Al sputtering Plasma etching SiO2 deposition Si3N4 Deposition SiO2 Deposition M13 Al sputtering Plasma etching SiO2 deposition Si3N4 deposition 2018/12/3 FCUECE_DGL_VLSIT
Layout design – Schematics INV NOR 2018/12/3 FCUECE_DGL_VLSIT
Layout Design – INV and NOR VDD VSS A OUT B VDD VSS IN OUT 2018/12/3 FCUECE_DGL_VLSIT
Devices on Wafer 2018/12/3 FCUECE_DGL_VLSIT
Logic Gates Layout - INV VDD VSS IN OUT VDD VSS IN OUT 2018/12/3 FCUECE_DGL_VLSIT
Logic Gates Layout – NOR VDD VSS A OUT B 2018/12/3 FCUECE_DGL_VLSIT
Role of Computer Technology CAD Virtual Fab / Fabless development Finding potential problems before fabrication Reducing developing time/costs 2018/12/3 FCUECE_DGL_VLSIT
Fabrication Equipment Crystal Growth Wafer Preparation Clean room Cleaning station Wafer carrier Pattern transferring Heat treatments Measurement 2018/12/3 FCUECE_DGL_VLSIT
Crystal Growth Vertical Horizontal 2018/12/3 FCUECE_DGL_VLSIT
Crystal Growth Czochralski method 2018/12/3 FCUECE_DGL_VLSIT
Crystal growth 2018/12/3 FCUECE_DGL_VLSIT
Crystal Growth Floating-zone method 2018/12/3 FCUECE_DGL_VLSIT
Crystal Growth Ingot 2018/12/3 FCUECE_DGL_VLSIT
Wafer Preparation Cutting Shaping Polishing 2018/12/3 FCUECE_DGL_VLSIT
Clean room 2018/12/3 FCUECE_DGL_VLSIT
Clean Room Factory 2018/12/3 FCUECE_DGL_VLSIT
Clean Room Factory 2018/12/3 FCUECE_DGL_VLSIT
Clean Room Garments 2018/12/3 FCUECE_DGL_VLSIT
Clean Room Production line 2018/12/3 FCUECE_DGL_VLSIT
Clean room Testing room 2018/12/3 FCUECE_DGL_VLSIT
Cleaning Station Wet bench 2018/12/3 FCUECE_DGL_VLSIT
Wafer Carrier 2018/12/3 FCUECE_DGL_VLSIT
Pattern Transferring Layout stream out Mask fabrication Transferring 2018/12/3 FCUECE_DGL_VLSIT
Pattern Transferring Resist inspection After Develop Inspection (ADI) Cross sectional view Top view 2018/12/3 FCUECE_DGL_VLSIT
Pattern Transferring Step and scan system Stepper 2018/12/3 FCUECE_DGL_VLSIT
Heat Treaments – Oxidation Furnace O2 H2O H2 + O2 HCl or TCA A cleaner RTO Real temperature is unknown 2018/12/3 FCUECE_DGL_VLSIT
Heat Treatments Diffusion Rapid Thermal Annealing 2018/12/3 FCUECE_DGL_VLSIT
Measurement Electron microscopy SiO2 Si 2018/12/3 FCUECE_DGL_VLSIT
References Fabrication Technology Vacuum Technology J. D. Plummer, M. D. deal, P.B. Griffin, “Silicon VLSI Technology – Funfamentals, Practice and Modeling,” Prentice Hall Inc., 2000(高立出版社). S. M. Sze, “VLSI Technology,” McGraw-Hill Book co., 1988(新月圖書公司). S. M. Sze, “Semiconductor Devices – Physics and Technology,” Bell Telephone Laboratories, Inc., 1985(中央圖書出版社). Vacuum Technology 呂登復,”實用真空技術,” 新竹黎明書店. Measurement Technology D. K. Schroder, “Semiconductor Material and Device Characterization,” John Wiley & Sons, Inc., 1990(臺北圖書公司). Journals Electronic Devices Society, IEEE IEEE Trans. Electron. Dev. IEEE Electron. Dev. Lett. Internat’l Electron. Dev. & Mater. (IEDM) Conference 2018/12/3 FCUECE_DGL_VLSIT