Processor Organization and Architecture Module III Processor Organization and Architecture

Instruction Formats Defines the layout of bits in an instruction Includes opcode & (implicit or explicit) operand(s) Usually more than one instruction format in an instruction set

Common Instruction Formats Four of them are Zero-address instruction One-address instruction Two-address instruction Three-address instruction

Zero-address instruction 0 (zero) addresses All addresses implicit Example: stack push a push b pop c 10

One-address instruction Implicit second address : Usually a register (accumulator) E.g. Add C // C=C+A(accumulator) 9

Two-address instruction 2 addresses One address doubles as operand and result a = a + b Reduces length of instruction Requires temporary storage to hold some results 8

Three-address instruction 3 addresses Operand 1, Operand 2, Result a = b + c; May be a forth - usually implicit Not common Needs very long words to hold everything 7

Key Design Issues of an Instruction Format

Instruction Length Programmers want More opcodes (to write short programs) More addressing modes (for flexibility in implementation of certain functions) Greater address range (more main memory) This results in longer instruction length (wasteful if 64 bit is used) Instruction length should be equal to memory transfer length or a multiple of it

Allocation of Bits More opcodes means more bits in the opcode field, which reduces the number of bits available for addressing Refinement : Variable length opcodes There is a minimum opcode length but for some opcodes, additional operations are specified by additional bits

Instruction Cycle Fetch: read the next instruction from memory to processor PC holds the address of the instruction to be fetched Unless told otherwise, PC is always incremented by 1 after each instruction fetch

Instruction Cycle Execute: Interpret the opcode and perform the indicated operation The fetched instruction is loaded into IR and performs the required action . Action falls into any of the following 4 categories Processor – Memory : Data transfer to/from memory Processor – I/O : Data transfer to/from I/O Data Processing Control : alter the sequence of execution

Indirect Cycle The operand specifier indicates whether an operand need to be fetched from memory which results in indirect addressing.

Instruction Cycle

A hypothetical machine

Instruction Cycle

Instruction Cycle State Diagram (without Interrupts)

Instruction Cycle State Diagram (without Interrupts) Address of the next instruction is calculated

Instruction Cycle State Diagram (without Interrupts) Reads instruction from memory

Instruction Cycle State Diagram (without Interrupts) Determines operation & operands to be used

Instruction Cycle State Diagram (without Interrupts) Determines address of operand

Instruction Cycle State Diagram (without Interrupts) Fetch operand from memory or I/O

Instruction Cycle State Diagram (without Interrupts) Perform the operation

Instruction Cycle State Diagram (without Interrupts) Determines address of result

Instruction Cycle State Diagram (without Interrupts) Store result in memory