Performance and RLC Crosstalk Driven Global Routing

Slides:



Advertisements
Similar presentations
Group: Wilber L. Duran Duo (Steve) Liu
Advertisements

A Graph-Partitioning-Based Approach for Multi-Layer Constrained Via Minimization Yih-Chih Chou and Youn-Long Lin Department of Computer Science, Tsing.
Optimization of Placement Solutions for Routability Wen-Hao Liu, Cheng-Kok Koh, and Yih-Lang Li DAC’13.
Topology-Aware Buffer Insertion and GPU-Based Massively Parallel Rerouting for ECO Timing Optimization Yen-Hung Lin, Yun-Jian Lo, Hian-Syun Tong, Wen-Hao.
Hsi-An Chien Ting-Chi Wang Redundant-Via-Aware ECO Routing ASPDAC2014.
Wen-Hao Liu1, Yih-Lang Li, and Cheng-Kok Koh Department of Computer Science, National Chiao-Tung University School of Electrical and Computer Engineering,
Meng-Kai Hsu, Sheng Chou, Tzu-Hen Lin, and Yao-Wen Chang Electronics Engineering, National Taiwan University Routability Driven Analytical Placement for.
Ripple: An Effective Routability-Driven Placer by Iterative Cell Movement Xu He, Tao Huang, Linfu Xiao, Haitong Tian, Guxin Cui and Evangeline F.Y. Young.
Coupling-Aware Length-Ratio- Matching Routing for Capacitor Arrays in Analog Integrated Circuits Kuan-Hsien Ho, Hung-Chih Ou, Yao-Wen Chang and Hui-Fang.
1 EL736 Communications Networks II: Design and Algorithms Class8: Networks with Shortest-Path Routing Yong Liu 10/31/2007.
Minimal Skew Clock Synthesis Considering Time-Variant Temperature Gradient Hao Yu, Yu Hu, Chun-Chen Liu and Lei He EE Department, UCLA Presented by Yu.
Layer Assignment Algorithm for RLC Crosstalk Minimization Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong Tsinghua University.
International Conference on Computer-Aided Design San Jose, CA Nov. 2001ER UCLA UCLA 1 Congestion Reduction During Placement Based on Integer Programming.
Localized Techniques for Power Minimization and Information Gathering in Sensor Networks EE249 Final Presentation David Tong Nguyen Abhijit Davare Mentor:
38 th Design Automation Conference, Las Vegas, June 19, 2001 Creating and Exploiting Flexibility in Steiner Trees Elaheh Bozorgzadeh, Ryan Kastner, Majid.
ER UCLA UCLA ICCAD: November 5, 2000 Predictable Routing Ryan Kastner, Elaheh Borzorgzadeh, and Majid Sarrafzadeh ER Group Dept. of Computer Science UCLA.
TH EDA NTHU-CS VLSI/CAD LAB 1 Re-synthesis for Reliability Design Shih-Chieh Chang Department of Computer Science National Tsing Hua University.
A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield A. B. Kahng, B. Liu, X. Xu, J. Hu* and G. Venkataraman*
Merging Synthesis With Layout For Soc Design -- Research Status Jinian Bian and Hongxi Xue Dept. Of Computer Science and Technology, Tsinghua University,
Processing Rate Optimization by Sequential System Floorplanning Jia Wang 1, Ping-Chih Wu 2, and Hai Zhou 1 1 Electrical Engineering & Computer Science.
A Resource-level Parallel Approach for Global-routing-based Routing Congestion Estimation and a Method to Quantify Estimation Accuracy Wen-Hao Liu, Zhen-Yu.
Metal Layer Planning for Silicon Interposers with Consideration of Routability and Manufacturing Cost W. Liu, T. Chien and T. Wang Department of CS, NTHU,
1 Enhancing Performance of Iterative Heuristics for VLSI Netlist Partitioning Dr. Sadiq M. Sait Dr. Aiman El-Maleh Mr. Raslan Al Abaji. Computer Engineering.
RLC Interconnect Modeling and Design Students: Jinjun Xiong, Jun Chen Advisor: Lei He Electrical Engineering Department Design Automation Group (
CDCTree: Novel Obstacle-Avoiding Routing Tree Construction based on Current Driven Circuit Model Speaker: Lei He.
More Realistic Power Grid Verification Based on Hierarchical Current and Power constraints 2 Chung-Kuan Cheng, 2 Peng Du, 2 Andrew B. Kahng, 1 Grantham.
Placement by Simulated Annealing. Simulated Annealing  Simulates annealing process for placement  Initial placement −Random positions  Perturb by block.
1 Coupling Aware Timing Optimization and Antenna Avoidance in Layer Assignment Di Wu, Jiang Hu and Rabi Mahapatra Texas A&M University.
TSV-Aware Analytical Placement for 3D IC Designs Meng-Kai Hsu, Yao-Wen Chang, and Valerity Balabanov GIEE and EE department of NTU DAC 2011.
Wen-Hao Liu 1, Yih-Lang Li 1, and Kai-Yuan Chao 2 1 Department of Computer Science, National Chiao-Tung University, Hsin-Chu, Taiwan 2 Intel Architecture.
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing © KLMH Lienig 1 EECS 527 Paper Presentation High-Performance.
New Modeling Techniques for the Global Routing Problem Anthony Vannelli Department of Electrical and Computer Engineering University of Waterloo Waterloo,
1 Efficient Obstacle-Avoiding Rectilinear Steiner Tree Construction Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang National Taiwan.
1 ε -Optimal Minimum-Delay/Area Zero-Skew Clock Tree Wire-Sizing in Pseudo-Polynomial Time Jeng-Liang Tsai Tsung-Hao Chen Charlie Chung-Ping Chen (National.
Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building Yanfeng Wang, Qiang Zhou, Xianlong Hong, and Yici Cai Department of Computer Science and.
Radhamanjari Samanta *, Soumyendu Raha * and Adil I. Erzin # * Supercomputer Education and Research Centre, Indian Institute of Science, Bangalore, India.
Simultaneous Analog Placement and Routing with Current Flow and Current Density Considerations H.C. Ou, H.C.C. Chien and Y.W. Chang Electronics Engineering,
Routability-driven Floorplanning With Buffer Planning Chiu Wing Sham Evangeline F. Y. Young Department of Computer Science & Engineering The Chinese University.
LEMAR: A Novel Length Matching Routing Algorithm for Analog and Mixed Signal Circuits H. Yao, Y. Cai and Q. Gao EDA Lab, Department of CS, Tsinghua University,
1 L25 : Crosstalk-Concerned Physical Design (2) Jun Dong Cho Sungkyunkwan Univ. Dept. ECE Homepage :
High-Performance Global Routing with Fast Overflow Reduction Huang-Yu Chen, Chin-Hsiung Hsu, and Yao-Wen Chang National Taiwan University Taiwan.
A Fully Polynomial Time Approximation Scheme for Timing Driven Minimum Cost Buffer Insertion Shiyan Hu*, Zhuo Li**, Charles Alpert** *Dept of Electrical.
DAOmap: A Depth-optimal Area Optimization Mapping Algorithm for FPGA Designs Deming Chen, Jason Cong , Computer Science Department , UCLA Presented.
-1- Delay Uncertainty and Signal Criticality Driven Routing Channel Optimization for Advanced DRAM Products Samyoung Bang #, Kwangsoo Han ‡, Andrew B.
A Novel Timing-Driven Global Routing Algorithm Considering Coupling Effects for High Performance Circuit Design Jingyu Xu, Xianlong Hong, Tong Jing, Yici.
Optimal Relay Placement for Indoor Sensor Networks Cuiyao Xue †, Yanmin Zhu †, Lei Ni †, Minglu Li †, Bo Li ‡ † Shanghai Jiao Tong University ‡ HK University.
An O(bn 2 ) Time Algorithm for Optimal Buffer Insertion with b Buffer Types Authors: Zhuo Li and Weiping Shi Presenter: Sunil Khatri Department of Electrical.
Placement and Routing Algorithms. 2 FPGA Placement & Routing.
Worst Case Crosstalk Noise for Nonswitching Victims in High-Speed Buses Jun Chen and Lei He.
On-Chip Power Network Optimization with Decoupling Capacitors and Controlled-ESRs Wanping Zhang1,2, Ling Zhang2, Amirali Shayan2, Wenjian Yu3, Xiang Hu2,
Tabu Search Review: Branch and bound has a “rigid” memory structure (i.e. all branches are completed or fathomed). Simulated Annealing has no memory structure.
Andrew B. Kahng and Xu Xu UCSD CSE and ECE Depts.
Jason Cong, David Zhigang Pan & Prasanna V. Srinivas
2 University of California, Los Angeles
Jinghong Liang,Tong Jing, Xianlong Hong Jinjun Xiong, Lei He
Tong Jing, Ling Zhang, Jinghong Liang
Sheqin Dong, Song Chen, Xianlong Hong EDA Lab., Tsinghua Univ. Beijing
Jin-Yih Li Yih-Lang Li Computer & Information TSMC Science Department,
Performance Optimization Global Routing with RLC Crosstalk Constraints
Chapter 3b Static Noise Analysis
Chapter 3b Static Noise Analysis
Yiyu Shi*, Wei Yao*, Jinjun Xiong+ and Lei He*
Subset of Slides from Lei Li, HongRui Liu, Roberto Lu
EDA Lab., Tsinghua University
Yiyu Shi*, Jinjun Xiong+, Chunchen Liu* and Lei He*
Continuous Density Queries for Moving Objects
Fast Min-Register Retiming Through Binary Max-Flow
Chapter 3b Leakage Efficient Chip-Level Dual-Vdd Assignment with Time Slack Allocation for FPGA Power Reduction Prof. Lei He Electrical Engineering Department.
Jason Cong, David Zhigang Pan & Prasanna V. Srinivas
Under a Concurrent and Hierarchical Scheme
Presentation transcript:

Performance and RLC Crosstalk Driven Global Routing Ling Zhang, Tong Jing, Xianlong Hong, Jingyu Xu Jinjun Xiong, Lei He Dept. of CST, Tsinghua Univ Dept. of EE, UC, Los Angeles Speaker: Xianlong Hong

ISCAS 2004, Vancouver, Canada Outline Introduction & Previous Work Problem Formulations Our Algorithm: PO-GR Experimental Results & Discussions Conclusions 2018/12/3 ISCAS 2004, Vancouver, Canada

ISCAS 2004, Vancouver, Canada Introduction Device size shrinking and clock frequency increasing Coupling capacitance and inductance could not be ignored Longer delay and crosstalk caused by coupling effects Global routing with performance optimization becomes more important. 2018/12/3 ISCAS 2004, Vancouver, Canada

ISCAS 2004, Vancouver, Canada Previous Work(1) Noise modeling Sakurai model (T. Sakurai, C. Kobayashi, M. Node, 1993) LSK model for calculating coupling inductance (L. He, K. M. Lepak, 2000) Model for calculating noise voltage (K. M. Lepak, I. Luwandi, L. He, 2001) 2018/12/3 ISCAS 2004, Vancouver, Canada

ISCAS 2004, Vancouver, Canada Previous Work(2) Noise minimization Spacing in detailed routing phase (K. Chaudhary, A. Onozawa et al, 1993) Track permutation in detailed routing phase (T. Gao, C. L. Liu, 1996) Wire perturbation in detailed routing phase (P. Saxena, C. L. Liu, 1999) Crosstalk reduction after global routing phase (T. X. Xue, E. S. Kuh, D. F. Wang, 1997) (J. J. Xiong, J. Chen, J. Ma, L. He, 2002) Coupling capacitance crosstalk reduction in global routing phase (J. Y. Xu, T. Jing, X. L. Hong, L. Zhang, 2004, ASP-DAC) 2018/12/3 ISCAS 2004, Vancouver, Canada

ISCAS 2004, Vancouver, Canada Major Contributions An efficient crosstalk elimination algorithm based on Tabu search and shielding technology is proposed. Timing performance and routability are simultaneously considered at global routing level. By using LSK model, we take coupling inductance into consideration. 2018/12/3 ISCAS 2004, Vancouver, Canada

ISCAS 2004, Vancouver, Canada Outline Introduction & Previous Work Problem Formulations Our Algorithm: PO-GR Experimental Results & Discussions Conclusions 2018/12/3 ISCAS 2004, Vancouver, Canada

Problem Formulations(1)—Global Routing Problem GRC GRG e v 2 1 v Fig.1 Global Routing Graph(GRG) 2018/12/3 ISCAS 2004, Vancouver, Canada

Problem Formulations(2)—LSK Model Accurate calculation: Simplified calculation in LSK model: 1 K f(i) g(j) gl Ni Nj gr Wire order kij Kit for segment of net i in region t: (for all j sensitive to i) LSK, the total K value for net i: (for all t occupied by net i) Fig.2 LSK Model 2018/12/3 ISCAS 2004, Vancouver, Canada

Problem Formulations(3)—Tabu Search Outline: Step1. Select an initial solution xnow, and set Tabu list H=empty; Step2. While not meet the stop conditions do Generate a candidate list Can_N(xnow) from the neighborhood N(xnow,H) of xnow that doesn’t conflict with H; Select the best solution from Can_N(xnow):xnext; xnow=xnext; Update Tabu list H; End While Key factors: neighborhood Tabu object & Tabu length aspiration rule How to search efficiently How to choose properly How to set the reasonably 2018/12/3 ISCAS 2004, Vancouver, Canada

ISCAS 2004, Vancouver, Canada Outline Introduction & Previous Work Problem Formulations Our Algorithm: PO-GR Experimental Results & Discussions Conclusions 2018/12/3 ISCAS 2004, Vancouver, Canada

Our Algorithm: PO-GR—(1) Part 1: timing performance and routability Part 2: Crosstalk estimation and elimination Part 1 firstly generates an initial routing solution considering congestion and timing optimization Then, Part 2 eliminates the crosstalk from the solution by inserting shields and gets a mid-result Finally, regard the mid-result as input and send it to Part 1 for iterations 2018/12/3 ISCAS 2004, Vancouver, Canada

Our Algorithm: PO-GR—(2) 1. Call Part 1 to generate a minimum wire length initial solution X0 without congestion and timing violation; Call Part 2 to obtain X1 = CEE(X0); If no edge overflow in X1 then go to 4.; Else do go back to 1. to generate a new solution; Call Part 1 again to obtain congestion and timing optimized solution X2 from X1; 2. CEE 3. 4. pseudo code of PO-GR Fig.3 flow chart of PO-GR 2018/12/3 ISCAS 2004, Vancouver, Canada

Insert shield with specific method Part 2—CEE partition the LSK bound at each sink of a net into the GRG edges belonging to the source-sink paths. Insert shield with specific method Check each net to eliminate possible remnant crosstalk and delete unnecessary shields to minimize total area. Fig.4 flow chart of CEE 2018/12/3 ISCAS 2004, Vancouver, Canada

Crosstalk Elimination Based on Tabu Search(1) Simulated Annealing, or Tabu search? The runtime of Simulated Annealing could be very long, while with similar performance, Tabu search is much faster. 2018/12/3 ISCAS 2004, Vancouver, Canada

ISCAS 2004, Vancouver, Canada xcur: current solution; xnew: candidate in neighborhood of xcur; xtmp: best candidate; xmin: best solution ever reached; Na: maximum iteration times with no improvement; Nb: number of candidates selected from neighborhood; Nc: maximum trying times for searching one candidate; randommove(x): method of generate a candidate in neighborhood of x; cost(x): evaluation of solution x; Set the global solution in one GRG edge as initial solution xcur; Set Tabu list H=empty; a=0; c=0; While( a < Na ) tmpcost = ; b = 0; While (b < Nb ) xnew = xcur; randommove ( xnew ); If cost (xnew) is in H c++; If c < Nc, then continue; Else c = 0; If cost (xnew) < tmpcost, then xtmp = xnew; tmpcost = cost (xnew); b++; End While Insert xcur into H; xcur= xtmp; If cost (xcur) < cost (xmin), then xmin = xcur; a = 0; Else a++; Update H; 2018/12/3 ISCAS 2004, Vancouver, Canada

Crosstalk Elimination Based on Tabu Search(2) randommove(x): { swap two net randomly, move one net randomly, insert one shield randomly, remove one shield randomly } cost(x)=w1*c1 + w2*c2 + w3*c3 + w4*c4 c1: total number of nets that are adjacent to their sensitive nets; c2: total number of shields in a GRG edge; c3: summation of (Keff - Kth ) for all nets with Keff > Kth in a GRG edge; c4: total number of nets with (Keff > Kth) in a GRG edge. 2018/12/3 ISCAS 2004, Vancouver, Canada

ISCAS 2004, Vancouver, Canada Outline Introduction & Previous Work Problem Formulations Our Algorithm: PO-GR Experimental Results & Discussions Conclusions 2018/12/3 ISCAS 2004, Vancouver, Canada

ISCAS 2004, Vancouver, Canada Benchmark Data Circuits Number of nets Grids   C2 745 9  11 C5 1764 16  18 C7 2356 Technology: 0.2um Sensitivity rate: 0.5 for all nets and sensitivity matrix is random. LSK bound:1000 at each sink 2018/12/3 ISCAS 2004, Vancouver, Canada

Experimental Results(1) Circuits C2 C5 C7 Step 2 in CEE Simulated Annealing(SA) 901.97 2140.36 3748.78 Tabu search 45.75 112.87 237.80 Runtime reduction 856.22 2027.49 3510.98 Step 3 in SA 153.53 56.36 453.70 91.44 34.08 227.50 62.09 22.28 226.20 Total runtime (Step2+Step3) 1055.50 2196.72 4202.48 137.19 146.95 465.30 Total runtime reduction 918.31 2049.77 3737.18 Comparison of runtime(s) between Tabu search and Simulate Annealing 2018/12/3 ISCAS 2004, Vancouver, Canada

Experimental Results(2) Circuits C2 C5 C7 Area SA 149196 271301 342395 Tabu search 149202 273307 346393 Shield number (Sn) 158 460 589 165 501 621 Sn increment 7 41 32 Comparison of results between Tabu search and Simulated Annealing 2018/12/3 ISCAS 2004, Vancouver, Canada

Experimental Results(3) Circuits C2 C5 C7 W mode (um) (Part 1)Wire length 480350 1307456 1552916 (PO-GR) Wire length 477326 1368198 1575922 Wire length increment -0.63% 4.65% 1.48% T mode 476424 1346876 1569366 479100 1280352 1567818 0.56% -4.94% -0.10% (Part 1) Min-R -0.009243 0.012124 0.000034 (PO-GR) Min-R -0.007195 0.003439 0.001243 Comparison of results between P1 and PO-GR 2018/12/3 ISCAS 2004, Vancouver, Canada

ISCAS 2004, Vancouver, Canada Discussions Tabu search sharply decreases the runtime of step2 in CEE(about 20x speedup), and doesn’t make any bad effects on step3 in CEE(its runtime slightly decreases too). Tabu search can obtains similar results in routing area compared with SA method, while the shielding number only increases a little. Tabu search achieve 2.5x wire length reduction compared with SA. PO-GR keeps the effectiveness in timing optimization. 2018/12/3 ISCAS 2004, Vancouver, Canada

ISCAS 2004, Vancouver, Canada Outline Introduction & Previous Work Problem Formulations Our Algorithm: PO-GR Experimental Results & Discussions Conclusions 2018/12/3 ISCAS 2004, Vancouver, Canada

ISCAS 2004, Vancouver, Canada Conclusions PO-GR is able to: Take coupling inductance into consideration. Tackle coupling noise, timing performance and routability simultaneously. Efficiently eliminate crosstalk throughout the global routing phase by inserting shields and has little influence on wire length and timing performance. Preserve the good routing result and greatly decrease the running time. 2018/12/3 ISCAS 2004, Vancouver, Canada

ISCAS 2004, Vancouver, Canada THANK YOU 2018/12/3 ISCAS 2004, Vancouver, Canada