FSM MODELING MOORE FSM MELAY FSM. Introduction to DIGITAL CIRCUITS MODELING & VERIFICATION using VERILOG [Part-2]

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Presentation transcript:

Introduction to DIGITAL CIRCUITS MODELING & VERIFICATION using VERILOG [Part-2]

FSM MODELING MOORE FSM MELAY FSM

MOORE FSM: Output is a function of present state only that are synchronized with the clock.

MELAY FSM: Output is a function of present state and inputs. When inputs change, outputs are updated immediately, without waiting for a clock edge. Outputs can be written more than once per clock cycle.

Problem Statement: Design a circuit that recognizes a sequence of three or more consecutive 1’s. State Diagram: Melay FSM Moore FSM

FSM Encoding Encoding the states is assigning unique binary numbers to the states. parameter initial = 3’b000, S1 = 3’b001, S2 = 3’b010, S3 = 3’b011, S4 = 3’b100 ; Choice of a particular encoding technique depends on “Area and Power” Constraints.

Moore FSM module Moore_FSM_RTL (y_out, x_in, clk, rst) ; input x_in, clk, rst ; output reg y_out ; //Binary State Encoding parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11 ; //state register reg [1:0] state ;

//Determine next state synchronously //based on present state and input. always @ (posedge clk or posedge rst) //sequential block begin if (rst) state <= S0 ; else case (state) S0: if (x_in) state <= S1 ; else state <= S0 ; S1: if (x_in) state <= S2 ; S2: if (x_in) state <= S3 ; S3: if (x_in) state <= S3 ; endcase end Use “Non-Blocking” assignment for Sequential block.

//output depends only on the state. always @ (state) //combinational block begin case (state) S0: if (x_in) y_out = 1'b0 ; else y_out = 1'b0 ; S1: if (x_in) y_out = 1'b0 ; S2: if (x_in) y_out = 1'b0 ; S3: if (x_in) y_out = 1'b1 ; endcase end endmodule Use “Blocking” assignment for Combinational block.

Synthesis – RTL View

Output Y: 0  1  0

Output Y: 1 0  1

Effect of “reset” input

Effect of “glitches” in the input

Moore FSM Output waveform

Melay FSM module Melay_FSM_RTL (y_out, x_in, clk, rst) ; input x_in, clk, rst ; output reg y_out ; //Binary State Encoding parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10 ; //state register reg [1:0] state ;

//determine next state synchronously //based on present state and input. always @ (posedge clk or posedge rst) //sequential block begin if (rst) state <= S0 ; else case (state) S0: if (x_in) state <= S1 ; else state <= S0 ; S1: if (x_in) state <= S2 ; S2: if (x_in) state <= S2 ; endcase end Use “Non-Blocking” assignment for Sequential block.

//Determine output only based on input and //present state. Don’t wait for clock edge. always @ (state or x_in) //combinational block begin case (state) S0: if (x_in) y_out = 1’b0 ; else y_out = 1’b0 ; S1: if (x_in) y_out = 1’b0 ; S2: if (x_in) y_out = 1’b1 ; endcase end endmodule Use “Blocking” assignment for Combinational block.

Synthesis – RTL View

Output Y: 0  1  0

Output Y: 1  0  1

Effect of “reset” input

Effect of “glitches” in the input

Melay FSM Output waveform

Comparison of Moore & Melay FSM output waveform

FSM Modeling Guidelines Use “parameters” to define state encodings. Use two “always” block coding style. Code all “sequential” always blocks using “non-blocking” assignments. Code all “combinational” always blocks using “blocking” assignments.