FPGA Tools Course Answers

Design Entry Answers What function does the CB4CLE perform? The CB4CLE is a 4 bit binary counter with clear, load and clock enable. Priority is: Clear (highest), clock enable (lowest). Name one example of a special component from the Xilinx Unified Library. High speed/low skew clocks, boundary scan, global reset network, on-chip oscillator The best way for a synthesis user to control the specific architectural features used in a design is by instantiating a component. True

LogiBLOX GUI and the Core Generator Answers Arithmetic functions can use what special resource to improve performance and density? Carry Logic What advantage is there in using a LogiBLOX Ram rather than a Ram from the Xilinx Unified Library? LogiBLOX will create the necessary decode and mux logic necessary for a large Ram. AllianceCOREs are created, tested, sold, and supported by Xilinx’s AllianceCORE partners. True

Report Browser (1) What are the main functions of the Translate and Map programs? Translate: To merge input netlist into one large file. Map: To translate logic into physical components, and group physical components into CLBS, or internal logic resources. What is the difference between the Logic Level Timing Report and the Post-Layout Timing Report? Logic Level is created before PAR with estimated (minimal) delays. Post-layout delays are based on placement and routing. What information is found in each file? Logic Level data is used to evaluate constraints. Are they realistic? Post-layout data is used to evaluate design performance.

Report Browser (2) Which file would you use to find the following: Percent of the FPGA used by your design? MAP report Did your design completely route? PAR report Did your design meet constraints? Logic Level Timing Report

Basic Timing Constraints Answers NET CLK PERIOD = 50; NET D1 OFFSET = IN 31 AFTER CLK; NET O1 OFFSET = OUT 27 BEFORE CLK;

Timing Analyzer Answers How do you determine what the longest delay path is in a design? Generate a Custom report with no specified paths. How can you be certain that all timing constraints were met? Generate a Report Paths in Timing Constraints report. If a PERIOD constraint of 20 ns is specified, and you find a maximum delay path from any node/to any node of 30 ns, could all of the constraints have been met? Yes, since the period constraint may only optimize pad-to-synchronous and synchronous-to-synchronous delay paths, the longest delay path may be on an output.

Hardware Optimization Summary (1) What problem may occur in this circuit? TC and Q may glitch during the transition of Q<0:2> from 011 to 100 D Q TC Q0 Q1 Q2 Binary Counter CK How can the circuit be improved? Carry-1 Q0 Q1 Q2 Binary Counter CE Q D TC CK TC will not glitch during the transition of Q<0:2> from 011 to 100

Hardware Optimization Summary (2) What does GSR stand for? What component sources the GSR net? Startup When should the GSR net be used? When all registers may be set/reset at the same time What component is instantiated to use the Global Clock? BUFG Can the Global Clock be synthesized? It depends on the synthesis tool. Synopsys, Exemplar, and Foundation (Express) synthesizers can all synthesize Global Clock buffers.

Hardware Optimization Summary (3) Why is one hot encoding a good way to encode a small state machine? One-hot works well since FPGAs have a large number of registers and the function generators are input limited. When should IOB registers be used? When you need a small input or output delay. When should they be avoided? When combinatorial logic is needed between registers. For example, placing registers from a counter would cause slow performance. However, a shift register could fit well in the IOB registers.

Implementation Options Answers What is the difference between the Post Layout Timing Report and the Logic Limiting Timing Report? The Post Layout Timing Report provides a brief analysis of the designs’ performance, while the Logic Level Timing Report will determine if the timing constraints are realistic. The Logic Level Timing Report uses estimated net delays. List three ways to increase speed of critical paths or overall design speed. Use timing constraints with design Increase the place and route effort level Use delay based cleanup Why should the number of routing passes be limited? If exit conditions are never met, the router will run until it decides it cannot complete routing.