Topics Circuit design for FPGAs: Logic elements. Interconnect.

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Presentation transcript:

Topics Circuit design for FPGAs: Logic elements. Interconnect.

Multiplexers as logic elements Q D CLR CLK latch 1 A B (AB)’ 1 A B A^B

Using antifuses

Static CMOS gate vs. LUT Number of transistors: Delay: Power: NAND/NOR gate has 2n transistors. 4-input LUT has 128 transistors in SRAM, 96 in multiplexer. Delay: 4-input NAND gate has 9t delay. SRAM decoding has 21t delay. Power: Static gate’s power depends on activity. SRAM always burns power.

Lookup table circuitry Demultiplexer or multiplexer? adrs LUT LUT adrs

Traditional RAM/ROM Cell drives long bit line: Bit line adrs

Lookup memory Multiplexer presents smaller load to memory cells. Allows smaller memory cells.

Multiplexer styles static gates pass transistors

Multiplexer design Pass transistor multiplexer uses fewer transistors than fully complementary gates. Pass transistor is somewhat faster than complementary switch: Equal-strength p-type is 2.5X n-type width. Total resistance is 0.5X, total capacitance is 3.5X. RC delay is 0.5 x 3.5 = 1.75 times n-type switch.

Static gate four-input mux Delay through n-input NAND is (n+2)/3. Lg b + 1 inputs at first level, so delay is (lg b + 3)/3. Delay at second level is (b+2)/3. Delay grows as b lg b.

Pass-transistor-based four-input mux Must include decode logic in total delay.

Tree-based four-input mux Delay proportional to square of path length. Delay grows as lg b2.

LE output drivers Must drive load: Wire; Destination LE. Different types of wiring present different loads.

Avoiding programming hazards Want to disable connections to routing channel before programming. From LE config progb Routing channel

Interconnect circuits Why so many types of interconnect? Provide a choice of delay alternatives. Sources of delay: Wires. Programming points.

Styles of programmable interconnection point pass transistor Three-state

Pass transistor programmable interconnect point Small area. Resistive switch. Delay grows as the square of the number of switches.

Three-state programmable interconnection point Larger area. Regenerative driver. +

Switch area * wire delay vs. buffer size (Betz & Rose) © 1999 IEEE

Switch area * wire delay vs. pass transistor width (Betz & Rose) © 1999 IEEE

Wire delay vs. switch sizes (Chandra and Schmidt) Delay vs. switch size for various driver sizes. U-shaped curve: Resistance initially decreases. Increased capacitance eventually dominates. © 2002 IEEE

Clock drivers Clock driver tree:

Clock nets Must drive all LEs. Design parameters: number of fanouts; load per fanout; wiring tree capacitance. Determine optimal buffer sizes.

H tree Regular layout structure. Recursive.