Figure 8.1 Architecture of a Simple Computer System.

Figure 8.2 Simple mP 1 Computer Instruction Format.

Figure 8.3 Basic mP 1 Computer Instructions.

Assembly Language MachineLanguage LOAD B 0211 ADD C 0012 STORE A 0110 Figure 8.4 Example Computer Program for A = B + C.

Figure 8.5 Processor Fetch, Decode and Execute Cycle.

Figure 8.6 Detailed View of Fetch, Decode, and Execute for the mP 1 Computer Design.

Figure 8. 7 Datapath used for the mP 1 Computer Design Figure 8.7 Datapath used for the mP 1 Computer Design. Values shown after applying reset.

Figure 8.8 Register transfers in the ADD instruction’s Fetch State.

Figure 8.9 Register transfers in the ADD instruction’s Decode State.

Figure 8.10 Register transfers in the ADD instruction’s Execute State.

Figure 8.12 MIF file containg mP 1 Computer Program.

Figure 8.13 Simulation of the Simple mP 1 Computer Program.