Day 27: November 6, 2013 Dynamic Logic ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 27: November 6, 2013 Dynamic Logic Midterm 2 Avg: 53 Std Dev.: 17 Penn ESE370 Fall2013 -- DeHon
Today Clocking Dynamic (Clocked) Logic Strategy Form Compare CMOS Penn ESE370 Fall2013 -- DeHon
Clocking Penn ESE370 Fall2013 -- DeHon
Clocking Highlights Clock discipline simplifies logic composition Abstracts many internal timing details Just concerned with making clock period long enough Breaking logic up with registers allows to run at high frequency – reuse logic Discipline – keeping data stable around clock edge Setup, hold time – determined by circuit ClkQ delay for data come out of register Penn ESE370 Fall2013 -- DeHon
Clocking Circuits typically operate in a clocked environment Gives some additional structure we can exploit Penn ESE370 Fall2013 -- DeHon
Dynamic Logic Penn ESE370 Fall2013 -- DeHon
Motivation Like to avoid driving pullup/pulldown networks reduce capacitive load Power, delay Penn ESE370 Fall2013 -- DeHon
Motivation Like to avoid driving pullup/pulldown networks reduce capacitive load Power, delay Ratioed had problems with Large device for ratioing Slow pullup Static power Penn ESE370 Fall2013 -- DeHon
Idea Use clock to disable pullup during evaluation Penn ESE370 Fall2013 -- DeHon
Discuss Use clock to disable pullup during evaluation What happens when /Pre=0, A=B=0 /pre=1, A=B=0? /pre=1, A=1, B=0? Sizing implication? Concerns? Requirements? Penn ESE370 Fall2013 -- DeHon
Advantages Large device Single network Driven by clock not data/logic Can pullup quickly w/out putting load on logic Single network Pulldown Don’t have to size for ratio with pullup Swings rail-to-rail Penn ESE370 Fall2013 -- DeHon
Domino Logic Penn ESE370 Fall2013 -- DeHon
Domino AND-OR Penn ESE370 Fall2013 -- DeHon
Domino Everything charged high After inverter all inputs low Why do we want this? Disabled, waiting for an enabling transition Penn ESE370 Fall2013 -- DeHon
Requirements Single transition All inputs at 0 during precharge Once fires, it is done like domino falling All inputs at 0 during precharge Precharge to 1 so inversion makes 0 Non-inverting gates http://en.wikipedia.org/wiki/File:Domino_effect.jpg Penn ESE370 Fall2013 -- DeHon
Issues Noise sensitive Power? Activity? Penn ESE370 Fall2013 -- DeHon
Domino or4 Penn ESE370 Fall2013 -- DeHon
Domino Logic Performance Compare to CMOS cases? R0/2 input nor4 or4 nand4 Penn ESE370 Fall2013 -- DeHon
Dynamic OR4 Precharge time? Driving input With R0/2 Driving inverter and self cap? Output self delay? Penn ESE370 Fall2013 -- DeHon
CMOS NOR4 Driving input Driving self cap? With R0/2 Penn ESE370 Fall2013 -- DeHon
CMOS NAND4 Driving input Driving self cap? w/ R0/2 Penn ESE370 Fall2013 -- DeHon
Discuss (time permit) Avoid inversion? Converting from CMOS? Post-charge Penn ESE370 Fall2013 -- DeHon
Observe Better (lower) ratio of input capacitance to drive strength Particularly good for Driving large loads Large fanin gates Harder to design with Timing and polarity restrictions Avoiding noise Especially with today’s high variation tech. Can consume more energy/op Penn ESE370 Fall2013 -- DeHon
Admin Homework 7 out Withdraw date Friday …and due on Tuesday Penn ESE370 Fall2013 -- DeHon
Idea Dynamic/clocked logic Only build/drive one network Fast transition propagation Spend delay (capacitance) on pullup off critical path of logic More complicated, power Reserve for when most needed Penn ESE370 Fall2013 -- DeHon