Design of Combinational Logic

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Presentation transcript:

Design of Combinational Logic Using CMOS

Combinational Logic with CMOS Representation of Binary variable Structure of CMOS gates Design of Combinational logic Using CMOS

Representation of Binary variable VHmax ‘ 1 ’ Transmitting Receiving VHmin Forbidden region VLmax ‘ 0 ’ VLmin

Structure of CMOS gate Output Need 2 sets of CMOS VH = ‘1’ and VL = ‘0’ Need 2 sets of CMOS o/p = VH -> switch output to VH o/p = VL -> switch ouput to VL VH PMOS VOUT Vin NMOS VL

Structure of CMOS gate PMOS PMOS NMOS VH VL Vin VOUT NMOS

Combinational Logic PMOS NMOS VH VL Vin VOUT VH VL Vin VOUT Pull-down network PDN Pull-up network PUN

Combinational Logic PMOS Pull-up network ON OFF VG = ‘0’ Vout = VDD Pull-up to VDD OFF VG = ‘1’ Vout = 0 Pull-down to GND ON for VG = ‘0’ -> Vout = ‘1’ Vout VDD RDS NMOS Vout VDD RDS NMOS

Combinational Logic NMOS Pull-down network ON OFF VG = ‘1’ Vout = 0 Pull-down to GND OFF VG = ‘0’ Vout = VDD Pull-up to VDD ON for VG = ‘1’ -> Vout = ‘0’ Vout VDD RDS PMOS RDS PMOS VDD Vout

Combinational Logic Design PMOS NMOS Check case: VG = ‘0’, Vout = ‘1’ Cascade structure Design PMOS Check case: VG = ‘0’, Vout = ‘1’ NMOS Check case: VG = ‘1’, Vout = ‘0’ y VDD

Combinational Logic x (i/p) = ‘0’ x (i/p) = ‘1’ PUN (PMOS) = ON y (o/p) = ‘1’ PDN (NMOS) = OFF x (i/p) = ‘1’ PUN (PMOS) = OFF PDN (NMOS) = ON y (o/p) = ‘0’ y VDD

Design Combinational Logic Design PMOS connection from Condition of y = ‘1’ ดูว่า x (i/p) เป็น ‘0’ อย่างไรถึงจะทำให้ y (o/p) = ‘1’ If the relation of x inputs is ‘and’ -> use cascade structure ‘or’ -> use parallel structure Design NMOS connection from Condition of y = ‘0’ ดูว่า x (i/p) เป็น ‘1’ อย่างไรถึงจะทำให้ y (o/p) = ‘0’

CMOS Inverter x y y VDD x

CMOS NAND Gate A B Out 1 Out = 1, When A = 0 or B = 0 1 Out = 1, When A = 0 or B = 0 In = 0, Out = 1 -> PMOS parallel Out = 0, When A = 1 and B = 1 In = 1, Out = 0 -> NMOS cascade

CMOS NOR Gate A B Out 1 Out = 1, When A = 0 and B = 0 Out 1 Out = 1, When A = 0 and B = 0 Out In = 0, Out = 1 -> PMOS cascade B Out = 0, When A = 1 or B = 1 In = 1, Out = 0 -> NMOS parallel