EEL 3705 / 3705L Digital Logic Design

Slides:

Advertisements

Similar presentations

ADDER, HALF ADDER & FULL ADDER

Advertisements

Modular Combinational Logic

ECE 3110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices XOR, Parity Circuits, Comparators.

1 ALUs. 2 Topics: ALU Overview - core of the integer datapath - 2 operands, 32-bits wide, plus control signals Exercise: A simple multiplier.

Arithmetic CPSC 321 Computer Architecture Andreas Klappenecker.

1 COMP541 Datapaths II Montek Singh Mar 22, 2007.

Computer ArchitectureFall 2008 © August 25, CS 447 – Computer Architecture Lecture 3 Computer Arithmetic (1)

Computer ArchitectureFall 2007 © August 29, 2007 Karem Sakallah CS 447 – Computer Architecture.

Computer Science 210 Computer Organization The Arithmetic Logic Unit.

Adders, subtractors, ALUs

Click to edit Master title style Click to edit Master text styles –Second level Third level –Fourth level »Fifth level 1 Today’s Topics How information.

ADDERS Half Adders Recall that the basic rules of binary addition are as indicated below in Table 2-9. A circuit known as the half-adder carries out these.

Chapter 6-1 ALU, Adder and Subtractor

ECE 3110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices Adders, subtractors, ALUs.

ECEN 248 Lab 4: Multiplexer Based Arithmetic Logic Unit

Instructor: Alexander Stoytchev CprE 281: Digital Logic.

Bits, Data types, and Operations: Chapter 2 COMP 2610 Dr. James Money COMP

ECE 3110: Introduction to Digital Systems Chapter 5 Combinational Logic Design Practices X-OR gates and Parity circuits Comparators Adders, subtractors,

1 Lecture 6 BOOLEAN ALGEBRA and GATES Building a 32 bit processor PH 3: B.1-B.5.

EE2174: Digital Logic and Lab Professor Shiyan Hu Department of Electrical and Computer Engineering Michigan Technological University CHAPTER 8 Arithmetic.

Universal college of engineering & technology. .By Harsh Patel)

A four function ALU A 00 ADD B MUX SUB 11 Result AND OR

The Karnaugh Map.

1 Understand the examples again Overflow –When two positive numbers added together or a negative number subtracted from a positive number yields negative.

EEL-3705 TPS QUIZZES Chapter 4. Quiz 4-1 Using the 2x4 Decoder shown below and two-input OR gates, design a logic circuit which implements.

COMPUTER ARCHITECTURE TRUTH TABLES AND LOGIC GATES.

1  2004 Morgan Kaufmann Publishers Lets Build a Processor Almost ready to move into chapter 5 and start building a processor First, let’s review Boolean.

ECE DIGITAL LOGIC LECTURE 5: BINARY LOGIC AND DIGITAL LOGIC GATES Assistant Prof. Fareena Saqib Florida Institute of Technology Fall 2016, 01/28/2016.

Number Representation (Part 2) Computer Architecture (Fall 2006)

Instructor: Alexander Stoytchev CprE 281: Digital Logic.

Lecture #23: Arithmetic Circuits-1 Arithmetic Circuits (Part I) Randy H. Katz University of California, Berkeley Fall 2005.

1 Arithmetic Where we've been: –Abstractions: Instruction Set Architecture Assembly Language and Machine Language What's up ahead: –Implementing the Architecture.

1 Ethics of Computing MONT 113G, Spring 2012 Session 4 Binary Addition.

Computer Arthmetic Chapter Four P&H. Data Representation Why do we not encode numbers as strings of ASCII digits inside computers? What is overflow when.

1 CS 151 : Digital Design Chapter 4: Arithmetic Functions and Circuits 4-3 : Binary Subtraction.

MIPS ALU. Exercise – Design a selector? I need a circuit that takes two input bits, a and b, and a selector bit s. The function is that if s=0, f=a. if.

Simple ALU  Half adder  Full adder  Constructing 4 bits adder  ALU does several operations  General ALU structure  Timing diagram of adder  Overflow.

9/23/2004Comp 120 Fall September Chapter 4 – Arithmetic and its implementation Assignments 5,6 and 7 posted to the class web page.

ECE 3110: Introduction to Digital Systems Chapter 5 Combinational Logic Design Practices Adders,subtractors, ALUs.

1 Chapter 4: Arithmetic for Computers (Part 2) CS 447 Jason Bakos.

REGISTER TRANSFER AND MICROOPERATIONS

Computer Arthmetic Chapter Four P&H.

Combinational Circuits

REGISTER TRANSFER AND MICROOPERATIONS

Instructor: Alexander Stoytchev

Computer Science 210 Computer Organization

CS221: Digital Logic Design Combinational Circuits 3

EEL 3705 / 3705L Digital Logic Design

EEL 3705 / 3705L Digital Logic Design

EEL 3705 / 3705L Digital Logic Design

Instructors: Randy H. Katz David A. Patterson

Computer Organization and Design Arithmetic & Logic Circuits

Computer Organization and Design Arithmetic & Logic Circuits

Arithmetic Where we've been:

Computer Organization and Design Arithmetic & Logic Circuits

EEL 3705 / 3705L Digital Logic Design

COSC 2021: Computer Organization Instructor: Dr. Amir Asif

EEL 3705 / 3705L Digital Logic Design

Instructor: Alexander Stoytchev

Instructor: Alexander Stoytchev

Instructor: Alexander Stoytchev

Instructor: Alexander Stoytchev

Multiple function unit design

Combinational Circuits

Instructor: Alexander Stoytchev

Computer Organization and Design Arithmetic Circuits

Presentation transcript:

EEL 3705 / 3705L Digital Logic Design Fall 2006 Instructor: Dr. Michael Frank Module #11: Signed arithmetic HW and ALUs (Thanks to Dr. Perry for some slides) 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Subtraction Circuit 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Subtraction Circuit Calculate 2’s complement of B Add –B to A 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Add/Sub Circuit 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Add/Sub Circuit Module 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Function Table for Add/Sub Module Functional Result S=A+B 1 S=A-B Add is a control input. It is active low. This means that the module will compute A+B when Add=0. It will compute A-B when Add=1. 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Add/Sub Circuit Design using Modules 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Add/Sub Circuit 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Add/Sub Circuit Add operation. Add=0 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Add/Sub Circuit Sub operation. Add=1 1 1 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Comparators 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Equal Comparator Design a logic circuit which will compute F0 = (A = B) 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

2-bit Equal Comparator Truth Table F0 1 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

2-bit Equal Comparator Truth Table F0 1 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Solution You can show, 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

N-bit Equal Comparator 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Not Equal Comparator Design a logic circuit which will compute F = (A <> B) F = (A = B) i.e. Just invert our Equal Comparator circuit 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Magnitude Comparator Design a logic circuit which will compute F2 = (A>B) F1 = (A<B) Let’s develop a truth table for 2-bits 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

2-bit Magnitude (unsigned) Comparator Truth Table F2 F1 1 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

2-bit Magnitude (unsigned) Comparator Truth Table F2 F1 1 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 You can show 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Arithmetic Logic Units (ALUs) 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Arithmetic Logic Unit (ALU) A,B are data inputs of n bits each in depth S is a control input. We have 2m operations F is the output 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Example Let n=4,m=3 We have A[3..0] and B[3..0] With m=3, we have 23 = 8 operations Let’s look at a possible function table 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Function Table s2 s1 s0 Function F=AB 1 F=A+B (logical OR) F=NOT A F=A XOR B F=A+B (Arithmetic) F=A-B F=A + 1 F=A - 1 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Design using a Truth Table How large is the truth table? 2n from data inputs A and B Example: n=8, we have 16 data inputs A[7..0] and B[7..0] 3 control inputs Total of 2n+3 inputs N=8, we have 19 inputs Our truth table will have 192 (361) rows and 8 outputs Too complex. Let’s explore another alternative using a “system” or modular approach 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Design using Modules Note: For S2=0, we have logic operations For S2=1, we have arithmetic operations So, let’s use S2 to control a 2x1 MUX to select between logic and arithmetic operations, so our top level design would look like: 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 ALU Design 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 ALU Design S2=0 With S2=0, F is the output from the logic module 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 ALU Design S2=1 With S2=1, F is the output from the arithmetic module 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Logic Module Design 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Function Table for Logic Module S2=0 s2 s1 s0 Function F=AB 1 F=A+B (logical OR) F=NOT A F=A XOR B We can use a 4x1 mux to implement this module 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Logic Module Design 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Logic Module Design F=AB AND Operation S[1..0]=00 0 0 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Logic Module Design F=A+B OR Operation S[1..0]=01 0 1 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Logic Module Design F=A NOT Operation S[1..0]=10 1 0 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Logic Module Design F=A XOR B XOR Operation S[1..0]=11 1 1 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

What do these logic modules look like? 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 AND Module 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 OR Module 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 NOT Module A F 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 XOR Module 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Let’s use our ADD/SUB Module Arithmetic Module Let’s use our ADD/SUB Module 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Add/Sub Circuit Module 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Function Table for Arithmetic Ops 1 F=A+B (Arithmetic) F=A-B F=A + 1 F=A - 1 Note: S0 can be use to indicate Addition or Subtraction. S1 can be use to indicate the B data input 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Arithmetic Module Design B A S 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Arithmetic Module Design B A S F=A+B S[1..0]=00 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Arithmetic Module Design B A S F=A-B S[1..0]=01 1 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Arithmetic Module Design B A S F=A+1 S[1..0]=10 1 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Arithmetic Module Design B A S F=A-1 S[1..0]=11 1 1 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Overall Design We have 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 ALU Design 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Logic Module Design 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

Arithmetic Module Design B A S 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 Total Design Logic Module Arithmetic Module 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006

M. Frank, EEL3705 Digital Logic, Fall 2006 End of Chapter 4 12/4/2018 M. Frank, EEL3705 Digital Logic, Fall 2006