Data Transfers To be able to implement Cond1: RD  RS Cond2: RS  RD together, we need a path from RD to RS and a path from RS to RD, each having m lines (for m-bit RD and RS) We can connect the output of RD to the input of RS in the previous circuit

Example: (op=1): R4← R3 + R2;

A 4-bit adder with registers on a bus

Implementing (op=1): R4← R3 + R2; Time step Operation to be performed (structural RTL) Control signals to be activated 1 A ← R3 LA, R3out 2 C ← A + R2 LC, R2out 3 R4 ← C LR4, Cout These steps have to be performed one after the other It indicates how the add operation is accomplished using the hardware shown before

ISA Design Steps Select suitable mnemonics for these operations add addi sub subi mul div and andi or ori not load store in out mov movi call ret int iret jpl jmi jnz jz jump nop reset halt shiftl shiftr asr

ISA Design Steps Assign op-codes add (0) addi (1) sub (2) subi (3) mul (4) div (5) and (8) andi (9) or (10) ori (11) not (14) load (29) store (28) in (24) out (25) mov (6) movi (7) call (22) ret (23) int (26) iret (27) jpl (16) jmi (17) jnz (18) jz (19) jump (20) nop (21) reset (30) halt (31) shiftl (12) shiftr (13) asr (15)

Op-code based listing of FALCON-A instructions 00000 add 00001 addi 00010 sub 00011 subi 00100 mul 00101 div 00110 mov 00111 movi 01000 and 01001 andi 01010 or 01011 ori 01100 shiftl 01101 shiftr 01110 not 01111 asr 10000 jpl 10001 jmi 10010 jnz 10011 jz 10100 jump 10101 nop 10110 call 10111 ret 11000 in 11001 out 11010 int 11011 iret 11100 store 11101 load 11110 reset 11111 halt

ISA Design Steps Assign fields to each operand in the instruction (at this time we can also decide on the instruction word length to be 16 bits) size of each field (depends on the number of registers also) let’s say eight GPRs => three bits to encode them encoding of the various fields straight binary encoding, shown on the next slide

Possible encoding of the GPRs Registers Encoding R0 000 R1 001 R2 010 R3 011 R4 100 R5 101 R6 110 R7 111

Skeleton Instruction Format Op-code ra rb rc unused 1 2 4 5 7 8 10 11 15 Variations of this skeleton format will yield the four types of instruction formats used in the FALCON-A

ISA Design Steps Decide on memory organization depends on size of PC and external data bus

ISA Design Steps Select instruction that are allowed to access memory Since FALCON-A is a RISC like machine, only load and store instructions are allowed to access memory

ISA Design Steps Select addressing modes (ways to access memory) Memory access in a load or store operation can be: Addressing Mode Format Example direct [constant or label] [10] or [a] displacement [register + constant or label] [R1 + 8] or [r2 + a] register indirect [register] [R3]

Programmer’s view of the FALCON-A 15 R0 R1 R7 Register file IR PC CPU : 7 7 1 1 2 2 : : 255 Input/Output 216-1 Main memory