CH7 Multilevel Gate Network Lecturer：吳安宇 教授 Date：2010/10/14 Version: v2

Outline 7.1 Multi-level Gate Circuits 7.2 NAND and NOR Gates 7.3 Two-level NAND- and NOR- Gate Network 7.4 Multi-level NAND- and NOR-gate Circuits 7.5 Circuit Conversion Using Alternative Gate Symbols 7.6 Design of Two-level Multiple-output Circuits 7.7 Multiple-Output NAND and NOR Circuits 台灣大學 吳安宇 教授

AND-OR and OR-AND Network AND-OR network : A two-level network composed of a level of AND gate followed by an OR gate at the output (SOP form) OR-AND network : A two-level network composed of a level of OR gate followed by an AND gate at the output (POS form) 台灣大學 吳安宇 教授

OR-AND-OR network OR-AND-OR network : A three-level network composed of a level of OR gates, followed by a level of AND gates, followed by an OR gate at output. 台灣大學 吳安宇 教授

Four-Level Realization of Z 4 levels 6 gates 13 gate inputs Figure 7-1 Four-Level Realization of Z 台灣大學 吳安宇 教授

Three-Level Realization of Z 3 levels 6 gates 19 gate inputs Figure 7-2: Three-Level Realization of Z 台灣大學 吳安宇 教授

Network of AND and OR gates Z = (AB+C)(D+E+FG)+H = AB(D+E)+C(D+E)+ABFG+CFG+H Gate input ; Cost Level ; Speed Trade-off among cost & speed ! 4 levels 6 gates 13 gate inputs 3 levels 6 gates 19 gate inputs 台灣大學 吳安宇 教授

EXAMPLE OF MULTI-LEVEL DESIGN (1/6) Find a network of AND and OR gates to realize f(a,b,c,d) = Σm(1,5,6,10,13,14) Consider solutions with two levels of gates and three levels of gates Try to minimize the number of gates and the total number of gate inputs. Assume that all variable and their complements are available as inputs. Solution: First simplify f by using Karnaugh map: (7-1) 台灣大學 吳安宇 教授

MULTI-LEVEL DESIGN (2/6) F = a’c’d + bc’d + bcd’ + acd’ This leads directly to a two-level AND-OR gate network 台灣大學 吳安宇 教授

MULTI-LEVEL DESIGN (3/6) Factoring (7-1) yields F = c’d(a’ + b) + cd’(a + b) (7-2) leads to three-level OR-AND-OR gate network (less gate inputs  lower cost  slower speed) 台灣大學 吳安宇 教授

EXAMPLE OF MULTI-LEVEL DESIGN (4/6) A two-level OR-AND network corresponds to a product-of-sums (POS) expression for the function. Obtained from the 0’s on the Karnaugh map: f’ = c’d’ + ab’c’ + cd + a’b’c (7-3) f = (c + d)(a’ + b + c) (c’ + d’)(a + b + c’) (7-4) (7-1) Eq. (7-4)  a two-level OR-AND network 台灣大學 吳安宇 教授

EXAMPLE OF MULTI-LEVEL DESIGN (5/6) To get a 3-level network with an AND gate output, we partially multiply out Eq. (7-4) using (X+Y)(X+Z) = X + YZ: f = [c + d(a’ + b)][c’ + d’(a + b)] (7-5) Eq. (7-5) would require 4 levels of gates to realize it. Multiply out d’(a + b) and d(a’ + b), we get (3 levels) f = (c + a’d + bd)(c’ + ad’ + bd’) (7-6) (7-6) 台灣大學 吳安宇 教授

EXAMPLE OF MULTI-LEVEL DESIGN (6/6) For this particular example: The best two-level solution has an AND gate at the output The best three-level solution had an OR gate at the output. In general, to be sure of obtaining a minimum solution, one must find both the network with the AND-gate output and the one with the OR-gate output. 台灣大學 吳安宇 教授

Outline 7.1 Multi-level Gate Circuits 7.2 NAND and NORGates 7.3 Two-level NAND- and NOR- Gate Network 7.4 Multi-level NAND, NOR-gate circuits 7.5 Circuit Conversion Using Alternative Gate Symbols 7.6 Design of Two-level Multiple-output 7.7 Multiple-Output NAND and NOR Circuits 台灣大學 吳安宇 教授

NAND gate General = F = (X1X2…Xn)’ = X1’+X2’+…+Xn’ F = (ABC)’ = A’ + B’ + C’ (DeMorgan’s Law) General = F = (X1X2…Xn)’ = X1’+X2’+…+Xn’ 台灣大學 吳安宇 教授

NOR gate F = (A+B+C)’ = A’ • B’ • C’ (DeMorgan’s Law) General form: F = (X1+X2+…+Xn)’ = X1’ •X2’ •… •Xn’ 台灣大學 吳安宇 教授

Majority and Minority Gates (seldom used) FM = a’bc + ab’c + abc’ + abc = bc + ac +ab Fm = (bc + ac + ab)’ = (b’ + c’)(a’ + c’)(a’ + b’) abc FM Fm M a b c FM 000 001 010 011 100 101 110 111 1 1 m a b c Fm 台灣大學 吳安宇 教授

Functionally Complete Set (1/5) A set of logic operations is functionally complete if any Boolean function can be expressed by this set. ex. {AND, OR, NOT} f = a’b + b’c + c’a ex. {AND, NOT} , OR? (X+Y) = [X’•Y’]’ = X+Y (DeMorgan) 台灣大學 吳安宇 教授

Functionally Complete Set (2/5) ex. {NAND} a. (X•X)’ = X’ (NOT) b. [(A•B)’]’ = AB (AND) c. [A’•B’]’ = A + B (OR) 台灣大學 吳安宇 教授

Functionally Complete Set (3/5) ex. {OR, NOT} and {NOR} Try by yourself! ex. {Minority gate} a bc 0 1 00 01 11 10 1 a b c Fm 4 5 6 7 1 0 0 1 0 1 1 1 0 1 1 1 1 2 3 0 0 0 0 0 1 0 1 0 0 1 1 m a b c Fm Fm = b’c’ + a’b’ + a’c’ 台灣大學 吳安宇 教授

Functionally Complete Set (4/5) ex. If Minority gate is functionally complete? (NOT) (AND) set A=1, F = B’C’= XY x m F = (X’•X’) + (X’•X’) + (X’•X’) = X’ X = B’ Y = C’ (a) m X Y 1 X’ Y’ (X’)’•(Y’)’ = X•Y 台灣大學 吳安宇 教授

Functionally Complete Set (5/5) (b) Set C = 0, F = A’ + B’, (A’ + B’)’ = AB (AND) m X Y X’ + Y’ (X’ + Y’) = XY (OR) m 1 X Y X’•Y’ (X’•Y’)’ = X+Y 台灣大學 吳安宇 教授

Outline 7.3 Two-level NAND- and NOR- Gate Network 7.4 Multi-level NAND, NOR-gate circuits 7.5 Circuit Conversion Using Alternative Gate Symbols 7.6 Design of Two-level Multiple-output 7.7 Multiple-Output NAND and NOR Circuits 台灣大學 吳安宇 教授

DeMorgan’s Law F = A + BC’ + B’CD = [(A+BC’+B’CD)’]’ (X1+X2+…+Xn)’ = X1’•X2’ •…•Xn’ (X1•X2•…•Xn)’ = X1’ + X2’ +…+Xn’ F = A + BC’ + B’CD = [(A+BC’+B’CD)’]’ = [ A’ • (BC’)’ • (B’CD)’ ]’ = [ A’ • (B’+C) • (B+C’+D’) ]’ = A + (B’+C)’ + (B+C’+D’)’ (AND-OR) (NAND-NAND) (OR-NAND) (NOR-OR) 台灣大學 吳安宇 教授

F = A + BC’ + B’CD = [(A+BC’+B’CD)’]’ = [A’ •(BC’)’ •(B’CD)’]’ Figure 7-14: Eight Basic Forms for Two-Level Networks 台灣大學 吳安宇 教授

To apply NOR-NOR gate (two-level) from POS form F = (A+B+C)(A+B’+C’)(A+C’+D) = { [(A+B+C)(A+B’+C’)(A+C’+D)]’ }’ = { (A+B+C)’ + (A+B’+C’)’ + (A+C’+D)’ }’ = ( A’B’C’ + A’BC + A’CD’)’ = (A’B’C’)’ • (A’BC)’ • (A’CD’)’ (OR-AND) (NOR-NOR) (AND-NOR) (NAND-AND) 台灣大學 吳安宇 教授

Eight Basic Forms for Two-Level Networks F = (A+B+C)(A+B’+C’)(A+C’+D) = {[(A+B+C)(A+B’+C’)(A+C’+D)]’}’ = {(A+B+C)’+(A+B’+C’)’+(A+C’+D)’}’ = (A’B’C’+A’BC+A’CD’)’ = (A’B’C’)’•(A’BC)’ •(A’CD’)’ Figure 7-14: Eight Basic Forms for Two-Level Networks 台灣大學 吳安宇 教授

Others AND-AND, OR-OR, OR-NOR, AND-NAND, NAND-NOR, NOR-NAND are degenerate ex. 台灣大學 吳安宇 教授

Minimum 2-level NAND-NAND network (1/2) (1) Find a minimum Sum-of-Product expression of F (2) Draw AND-OR (2-level) Network (3) Convert into NAND-NAND Network How about NOR-NOR?? (X’ + Y’) = (XY)’ A B C D A B C D F F A B C D F = AB + CD (SOP Form) F 台灣大學 吳安宇 教授

Procedure to design a minimum NAND-NAND network (two-level) (2/2) Fig.7-12 example (p.187) F = l1+ l2+ …+ P1 + P2+ … = (l1’ • l2’ •…• P1’ • P2’ •…)’ 台灣大學 吳安宇 教授

Procedure to design minimum 2-level NOR-NOR network Draw the two-level OR-AND network Find a minimum POS expression of F Replace all gates with NOR gates a b c d a b c d F F 台灣大學 吳安宇 教授

Outline 7.2 Other Types of Logic Gates 7.3 Two-level NAND- and NOR- Gate Network 7.4 Multi-level NAND, NOR-gate circuits 7.5 Circuit Conversion Using Alternative Gate Symbols 7.6 Design of Two-level Multiple-output 7.7 Multiple-Output NAND and NOR Circuits 台灣大學 吳安宇 教授

Procedure Simplify the switching function. Convert into multi-level AND-OR network. Output gate is level 1, mark all levels. Leave inputs to levels 2,4,6,…unchanged. Invert inputs to levels 1,3,5,… 台灣大學 吳安宇 教授

Gate Symbols 台灣大學 吳安宇 教授

Design example F1 = a’ [ b’ + c(d + e’) + f’g’ ] + hi’j + k 台灣大學 吳安宇 教授

Outline 7.2 Other Types of Logic Gates 7.3 Two-level NAND- and NOR- Gate Network 7.4 Multi-level NAND, NOR-gate circuits 7.5 Circuit Conversion Using Alternative Gate Symbols 7.6 Design of Two-level Multiple-output 7.7 Multiple-Output NAND and NOR Circuits 台灣大學 吳安宇 教授

Conversion of NAND gate network 台灣大學 吳安宇 教授

Conversion OR-AND to NOR Gates Figure 7-16 Conversion to NOR Gates Start with level 1 NOR Gate 台灣大學 吳安宇 教授

Conversion of AND-OR Circuit to NAND Gates (I) Even if AND and OR gates do not alternate, we can still convert an AND-OR circuit into a NAND-NOT-NAND circuit, but may need extra inverters. 台灣大學 吳安宇 教授

Conversion of AND-OR Circuit to NAND Gates (II) Figure 7-17 Conversion of Non- Alternating AND-OR Circuit into NAND Gates (1) 全部換成NAND gates! (2) Cannot cancel!!  Add Inverters NAND Gate (3) NAND gates Implement 台灣大學 吳安宇 教授

Outline 7.2 Other Types of Logic Gates 7.3 Two-level NAND- and NOR- Gate Network 7.4 Multi-level NAND, NOR-gate circuits 7.5 Circuit Conversion Using Alternative Gate Symbols 7.6 Design of Two-level Multiple-output 7.7 Multiple-Output NAND and NOR Circuits 台灣大學 吳安宇 教授

Design of a Logic Network with four inputs and three outputs (I) F1(A,B,C,D) = Σm(11,12,13,14,15) F2(A,B,C,D) = Σm(3,7,11,12,13,15) F3(A,B,C,D) = Σm(3,7,12,13,14,15) ACD CD A’CD AB AB 台灣大學 吳安宇 教授

Logic Network Realization (1/2) Direct Implementation 9 gates 21 gate inputs CD AB AB is shared (F1&F3) CD = A’CD + ACD (F1, F3  F2) 台灣大學 吳安宇 教授

Logic Network Realization (2/2) Note that AB is shared by F1 and F3 CD = ACD + A’CD = CD(A + A’) 7 gates 18 gate inputs  Use of a minimum SOP => minimum cost solution Guideline: Minimize the total number of gates. If the number of gates is the same, the one with minimum number of gate input is chosen. 台灣大學 吳安宇 教授

A 4-inputs/3-outputs design (II) f1 = Σm(2,3,5,7,8,9,10,11,13,15) f2 = Σm(2,3,5,6,7,10,11,14,15) f3 = Σm(6,7,8,9,13,14,15) (Figure 7-21) f1 f2 f3 bd (f1)  a’bd (f2) + abd (f3) (combine) ab’c’ (f1)  covered by ab’c’ (f3) (share) 台灣大學 吳安宇 教授

Example: A 4-inputs/3-outputs design If each function is minimized separately, => f1 = bd + ab’ + b’c f2 = c + a’bd f3 = bc + ab’c’ + Check K-map to see common minterms => f1 = a’bd + abd + ab’c’ + b’c f3 = bc + ab’c’ + abd 10 gates 25 gate inputs abd ac’d 8 gates 22 gate inputs 台灣大學 吳安宇 教授

Desgin Case (III) (Fig. 7.22) (a) NOT to combine 1 with adjacent 1’s (b) c’d is essential to f1 for multiple-output realization abd is not essential for multiple-output realization c’d abd But it is essential to f1 (cover m15) 台灣大學 吳安宇 教授

Design Case (IV) (Fig. 7.23) (a) Max number of common terms is not best (b) m2 = cover by a’d’ (essential to f1 & all) m5 = cover by a’bc (essential to f1 & all) m12 = cover by bd’ (essential to f2 & all) Basic rule: Identify EPI to all functions However, it cannot be applied to Fig. 7-21! Very difficult to find global optimal solution!! 台灣大學 吳安宇 教授

Summary (I) When designing multiple-output circuits, it is sometimes best to ‘not’ to combine a 1 with its adjacent 1’s, as shown in Fig.7-22. The solution with the maximum number of common terms is ‘not’ necessary best, as shown in Fig.7-23 台灣大學 吳安宇 教授

Summary (II) PI’s essential to an individual function may not be essential to the multiple-output realization. e.g. (Fig 7-22) bd is EPI to f1 (cover m5), but it is not essential (m5 also appear on f2 map). Modified procedure: check each 1 on the map to see if it is covered by only one PI. (Fig.7-22) cd’ is essential to f1 (cover m1) abd is not. (both f1 and f2) 台灣大學 吳安宇 教授

Summary (III) (Fig 7-23) m2 and m5 of f1 are not covered by f2 m2 is covered by f1 (a’d’), a’d’ is essential to f1 M5 is covered by a’bc’ of f2, a’bc’ is essential to f2 on f2 map, bd’ is essential (Why?) (Check) Once the EPI of f1 & f2 are looped, selection of the remaining terms to form thr minimum solution is obvious. (Fig 7-21) Every minterm of f1 are covered by f2 & f3  More sophisticated solution is needed 台灣大學 吳安宇 教授

7.7 Multiple-Output NAND and NOR Circuits If all of the output gates are OR gates, direct conversion to a NAND-gate circuit is possible. If all of the output gates are AND, direct conversion to a NOR-gate circuit is possible. Figure 7-24:1-output circuit to NOR gates. Note that the inputs to the first and third levels of NOR gates are inverted. F1 = [(a + b’)c + d](e’ + f) F2 = [(a + b’)c + g’](e’ + f)h Figure 7-24 台灣大學 吳安宇 教授