Organizacija adresnog prostora (2)

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Presentation transcript:

Organizacija adresnog prostora (2) 29.11.1996. Organizacija adresnog prostora (2) - Dekoderi (eksperiment) - Pojam adresne magistrale i magistrale podataka - Uprvaljačka magistrala - Logička i fizička adresa - Smeštanje periferijske jedinice u memorijski prostor - Manipulacije sa memorijskim prostorom - Harvardska i Fon Nojmanovska arhitektura - MMU (Memory Management Unit)

16-bitni adresni prostor D0-D7 Magistrala podataka A0-A15 Magistrala adresa

Magistrale adresa i podataka MREQ Memory Request OE Output Enable CS Chip Select CPU Central Processing Unit ROM Read Only Memory

Podela adresnog prostora

Mapiranje dva memorijska čipa

Dekoder 74HC138 A0, A1, A2 Adresni ulazi G1, G2, G3 Gate (upravljački) ulazi 0...7 Izlazi

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Podela adresnog prostora pomoću dekodera

Pozicija RAM-a u adresnom prostoru RAM Random Access Memory RD Read WR Write

Mapiranje memorija različitih kapaciteta

Fon Nojmanovska arhitektura mikroprocesora Programska memorija i memorija za podatke dele isti adresni prostor Moguće je izvršavanje programa iz memorije za podatke Postoji jedan glavni upravljački vod za sve memorije Moguće je smestiti ulazno-izlazne jedinice u zajednički adresni prostor

Upravljački signali za Fon Nojmanovsku arhitekturu

Primer definisanja sadržine memorije u asembleru