INTRODUCING MICROWIND

Slides:



Advertisements
Similar presentations
Embedded Systems Design: A Unified Hardware/Software Introduction 1 Chapter 10: IC Technology.
Advertisements

Design and Implementation of VLSI Systems (EN0160) Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley]
Design and Implementation of VLSI Systems (EN1600) lecture05 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison.
VLSI Lab References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially.
R. Kluit Electronics Department Nikhef, Amsterdam. Integrated Circuit Design.
EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Manufacturing Process Dr. Shiyan Hu Office: EERC 731 Adapted and modified from Digital Integrated.
CMOS Fabrication nMOS pMOS.
EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Manufacturing Process -II Dr. Shiyan Hu Office: EERC 518 Adapted and modified from Digital Integrated.
EE141 Manufacturing 1 Chapter 2 Manufacturing Process and CMOS Circuit Layout 1 st rev. : March 7, nd rev. : April 10, 2003.
05-1 Digital Integrated Circuits 05: Advanced Fabrication & Lithography Revision
Full-Custom Design ….TYWu
Introduction to CMOS VLSI Design Lecture 0: Introduction.
Microelectronic Circuit Design McGraw-Hill Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock.
TEACHING CMOS CIRCUIT DESIGN IN NANOSCALE TECHNOLOGIES USING MICROWIND
Introduction to ASICs ASIC - Application Specific Integrated Circuit
CHAPTER 4: MOS AND CMOS IC DESIGN
14NM FINFET IN MICROWIND.
IC Manufactured Done by: Engineer Ahmad Haitham.
Future trends in nano-CMOS cell design with Microwind
DREAM TEAM 2 Roto, Holiano, Chaka
THE CMOS INVERTER.
ROADMAP TO NANOMETER.
Chapter 3 Fabrication, Layout, and Simulation.
Manufacturing Process -II
MOS Field-Effect Transistors (MOSFETs)
Subject Name: Fundamentals Of CMOS VLSI Subject Code: 10EC56
MOS TRANSISTOR (Remind the basics, emphasize the velocity saturation effects and parasitics) Structure of a NMOS transistor.
Low Write-Energy STT-MRAMs using FinFET-based Access Transistors
STICK Diagrams UNIT III : VLSI CIRCUIT DESIGN PROCESSES VLSI DESIGN
THE MOS DEVICE.
20-NM CMOS DESIGN.
HW5: Mentor Graphics I “ Design of a CMOS Inverter”
14-NM TECHNOLOGY & FinFET in MICROWIND
TECHNOLOGY TRENDS.
Chapter 1 & Chapter 3.
Design Rule EMT 251.
AdMOS GmbH Advanced Modeling Solutions
VLSI Design MOSFET Scaling and CMOS Latch Up
Downsizing Semiconductor Device (MOSFET)
EE141 Chapter 3 VLSI Design The Devices March 28, 2003.
EE213 VLSI DesignStephen Daniels 2003 VLSI Design Design Rules EE213 VLSI Design.
Digital Integrated Circuits A Design Perspective
IC TECHNOLOGY.
Electrical Rules Check
An Illustration of 0.1µm CMOS layout design on PC
Chapter 10: IC Technology
LEC 3.2 LAYOUT D E S I G N R U L E S & DESIGN RULE CHECKER (DRC)
Lecture #25 OUTLINE Device isolation methods Electrical contacts to Si
Future trends in nano-CMOS cell design
DESIGN FOR MANUFACTURABILITY
Downsizing Semiconductor Device (MOSFET)
Introduction to Layout Inverter Layout Example Layout Design Rules
2. Introduction to Design Rules
VLSI Lay-out Design.
VLSI Design CMOS Layout
V.Navaneethakrishnan Dept. of ECE, CCET
Chapter 10: IC Technology
Implementation Technology
ECE 424 – Introduction to VLSI Design
DARE180U Platform Improvements in Release 5.6
EE216A – Fall 2010 Design of VLSI Circuits and Systems
CMOS Layers n-well process p-well process Twin-tub process.
Chapter 10: IC Technology
Beyond Si MOSFETs Part IV.
Unit -4 Introduction to Embedded Systems Tuesday.
Chapter 4 Field-Effect Transistors
Presentation transcript:

INTRODUCING MICROWIND

www.microwind.org WHAT IS MICROWIND Microwind is a unique educational tool for designing nano-CMOS cells Microwind may be configured in any technology from 1.2µm downto 14nm Microwind illustrates 2D, 3D aspects of Ics Microwind simulates cells & blocks using embedded simulator www.microwind.org

2006 – New Delhi 2006 – Pune www.microwind.org WHAT IS MICROWIND Books on CMOS basic & advanced design have been written by E. Sicard, S. Ben Dhia and published by Tata-McGrawHill in 2006 Microwind has been successfully deployed in India and in some universities around the world by ni2designs 2006 – Pune www.microwind.org

Acceptable for simulators MOS MODELS Microwind uses Level1, Level3, and a simplified version of BSIM4, adapted to FinFET “Typically, FinFET models have over 1,000 parameters per transistor, and more than 20,000 lines of C code” BSIM in Microwind uses 25 parameters and 250 lines of code… but makes many simplifications Bsim CMG Bsim6 Acceptable for simulators 1000 Bsim4 Bsim3 Bsim2 Bsim Model parameters 100 MM9 Level 2 Level 3 Acceptable for teachers 10 Level 1 Acceptable for students 1 1970 1980 1990 2000 2010 2020 Year

MICROWIND FEATURES FOLLOWING THE SCALE DOWN 2 supply Low K Double patterning Metal gate nMOS Strain Pocket implant pMOS Strain High K oxide 8 Metal Double gates

2nd generation strain, 10 metal layers NANO-CMOS APPLICATION NOTES Technology node   Year of introduction Key Innovations 90nm 2003 SOI substrate 65nm 2004 Strain silicon 45nm 2008 2nd generation strain, 10 metal layers 32/28nm 2010 High-K metal gate 20nm 2013 Replacement metal gate, Double patterning, 12 metal layers 14nm 2016 FinFET www.microwind.org > Application Notes

MICROWIND LAMBDA-BASED DESIGN Gate pitch Microwind works in lambda units (λ) Not optimum layout but independent of technology Design rules have remained nearly the same for 20 years λ is nearly half of technology (8nm in 14-nm node) Channel length is 2 λ Minimum gate pitch is 8 λ (2+6) Minimum metal pitch is 6 λ (3+3) Channel length Metal pitch

2500 1000 design rules DESIGN RULES Microwind DRC only checks around 100 basic design rules In 14-nm technology, more than 2500 design rules have been listed in the design kit Layouts cannot be fabricated without full DRC 130nm 500 design rules 65nm 1000 design rules 14nm 2500