Advanced Digital Design Introduction & Motivation by A. Steininger and M. Delvai Vienna University of Technology

© A. Steininger & M. Delvai / TU Vienna Outline Challenges in Digital Design The Role of Time in the Design The Fundamental Design Problem A Simple Communication Model Basic Design Strategies - Overview The Timed Communication Model Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna The market demands … … faster chips („performance“) … smaller chips („embedded“) … cheaper products („consumer prod.“) … more functions („features“) … battery supply („mobile“) … robust operation („reliable“) Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna Technology‘s Answer Miniaturization makes chips … … faster … smaller … cheaper … more complex & powerful … (ultimately) more power-hungry … more error-prone Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Vizualizing Miniaturization TODO: show squares with relative size for same circuit over the years… Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

The Chip Design Crisis short time-to-market hard physical limits impede miniaturization power delivery problems designer productivity gap increasing transient fault rates hard physical limits impede speed-up excessive test complexity heat problems increasing NRE costs Do we need a new („revolutionary“) design approach? Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna The MOS Transistor n-channel enhancement FET contacts gate oxide n+ substrate W L T OX channel Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

This is no more true for tech-nology nodes below 100nm! Scaling Theory „Scaling technology by a scales… area by 1/a2 transistor current by 1/a transistor power by 1/a2 power density (pwr/area) by 1 “ This is no more true for tech-nology nodes below 100nm! Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Static Power Consumption gate tunnel currents (currents over gate oxide)  grow exponentially for thinner oxide subthreshold currents (currents over „open“ transistor)  grow for lower threshold voltage leakage currents (currents over reverse biased junction)  can be decreased by SIO, e.g. Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Dynamic Power Consumption switching currents (loading parasitic capacitances) crowbar currents (imperfect stack switching) Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Power Consumption Trends processor power [W] 1000 100 dynamic 10 1 static 0.1 0.01 [Furuyama, DSD’06] 1960 1970 1980 1990 2000 2010 Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Limits of Miniaturization charge of an electron does not scale e = -1,602.10-19 C size of an atom does not scale Si-Atom = 0.05nm wave length for lithography does not scale lUV>150nm statistics of band model does not scale: invalid for small populations (doping) exponential growth of tunnel currents linear growth of electrical field strength … Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Fundam. Speed Limitations EM wave propagation Information can never travel faster than with speed of light. Charging effects Charging of a capacitance with limited current takes time. Charge movement Movement/diffusion of charges in a semiconductor occurs at limited speed. Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna EM Wave Propagation Electrical signals and their associated electromagnetical (EM) waves travel at the speed of light. In vacuum this speed is 3 x 108 m/s, that is approx. 109 km/h or 30cm/ns. In media the speed of light depends on mr and er and is always lower than in vacuum. A typical value for a cable is 2/3 of the speed of light, that is 20cm/ns. Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Fundam. Speed Limitations EM wave propagation Information can never travel faster than with speed of light. Charging effects Charging of a capacitance with limited current takes time. Charge movement Movement/diffusion of charges in a semiconductor occurs at limited speed. Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Capacitor Charging Process Step response of an RC lowpass exponential voltage curve Time Constant t determines timing scale is the product of R and C. Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna The RC-Charging Curve Uin UC t = RC Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna Delay caused by RC Delay  t 65% (Threshold) Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna Which R‘s and C‘s? Resistance (R) of the „conducting“ FET (Drain/Source) the interconnect (Al, Cu) the vias the programming elements Capacitance (C) of conducting parts mutually structures of one/different FETs interconnect Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Fundam. Speed Limitations EM wave propagation Information can never travel faster than with speed of light. Charging effects Charging of a capacitance with limited current takes time. Charge movement Movement/diffusion of charges in a semiconductor occurs at limited speed. Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna The Diffusion Process When opening/closing a FET switch charges must be removed from/moved to the channel. This occurs much slower than with the speed of light: The saturation value for the diffusion speed in silicon is 0.1mm/s, which is 36000 km/h, or 0.5% of the speed of light (in medium). Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Fundam. Speed Limitations EM wave propagation Information can never travel faster than with speed of light. Charging effects Charging of a capacitance with limited current takes time. Charge movement Movement/diffusion of charges in a semiconductor occurs at limited speed. Fundamental law of physics inevitable material-immanent Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna Resume 1 Propagation & processing of information is inevitably associated with a delay This delay may be minimized, but will never become zero. Although this delay appears to be very small, it constitutes the major limitation for the speed of digital circuits, therefore it IS relevant. Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Power Delivery Problems need to deliver currents of many amps into chip extreme current density in bondings & power rails need to supply huge current spikes within ps parasitic inductances critical buffer capacitances required noise margins reduced Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna Time-to-market needs to be ever shorter rapidly changing standards „last minute“ availability of crucial components/specs exploit market opportunities being late causes tremendous loss of profit Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna Productivity Gap log +59%/a (Moore) trans/chip trans/staff/time +21%/a t [ITRS] We cannot design as complex chips as we could manufacture need much better tool support need to combine pre-designed modules Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna TODO add scale to previous diagram (from ITRS) Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna Test & Verification 70% of time spent on verification It will soon cost more to test a transistor than to manufacture it log € cost/trans test costs  const -29%/a t [ITRS] Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna Transient Faults …occur 10…100 times more often than permanent faults today …originate from storage elements being upset …can only be caused by disturbances with an energy larger than that stored in the affected cell … are often caused by particle hits (single event upsets: SEUs) Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Fault Rate Predictions energy stored in a storage element scales with feature size power supply energy distribution of particles is non-linear significantly more particles towards lower energy fault potential largely increases with every technology node Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna Fault Mitigation stopping miniaturization is not an option technology (materials, shielding,…) keeps fault rate per transistor  constant = still overall increase per chip robust circuit design requires different design techniques system-level fault tolerance current solution expensive Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna Ideal Design Method An ideal design method … minimizes power consumption miminizes circuit overhead naturally supports composability naturally aids testability yields robust circuits yields fast circuits. Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna Solutions ahead? Many people envision a paradigm shift as the only solution As the pain grows… so does the willingness to perform such a shift so does the incentive to come up with a novel solution Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

The Role of Time in Digital Design Assumptions behind common practice

© A. Steininger & M. Delvai / TU Vienna Boolean Logic unambiguous time-free description combinational logic truth table, e.g. sequential logic state diagram, e.g. (sequence) independent of implementation temporal relations are not relevant (but for sequence) Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna Implementation There is a signal delay in all transistors through all interconnect this signal delay cannot be eliminated is indeterministic Why ? Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Fundam. Speed Limitations EM wave propagation Information can never travel faster than with speed of light. Charging effects Charging of a capacitance with limited current takes time. Charge movement Movement/diffusion of charges in a semiconductor occurs at limited speed. Fundamental law of physics inevitable material-immanent Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna Delay Contributors Gate Delay propagation delay through a logic element largely independent from routing quite predictable Interconnect Delay propagation delay on a signal line very dependent on routing scarcely predicatble Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna Delay Trends delay [ns] 1.0 gate interconnect 0.1 l [mm] 1.0 0.5 0.25 Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna Can we predict Delay? after synthesis: logic depth complexity of operation optimization & mapping after routing: interconnect geometrie (lengths, capacitances) vias, switches during operation: actual values process variations temperature supply voltage Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna Resume 2 Signal delay is not only extremely difficult to predict, it varies with the operating conditions. The delays along two individual signal paths will never be the exactly the same. The (maximum) difference among two or more signal paths of interest – which is termed „skew“ – is even more difficult to predict. Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna Skew and Consistency Data consistency When individual data items are interpreted together (to attain a more global, comprehensive view), these must belong to the same context: they must be temporally correlated Example: speeds of wheels combined to derive dynamic state of vehicle Skew distorts temporal correlation Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Consistency – an Example sending 00 10 11 01 00 Delay receiving 00 10 11 01 00 Skew receiving 10 00 01 00 receiving 00 10 11 01 00 Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Consistency & Glitches 1 Y = A  A  0  1 A 1 DT Everything OK for the steady state A dynamic analysis reveals glitches! Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna Boolean Logic unambiguous time-free description combinational logic truth table, e.g. sequential logic state diagram, e.g. (sequence) independent of implementation temporal relations are not relevant (but for sequence) cannot be expressed! Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna The Consequences Boolean Logic describes the I/O-mapping without consideration of time This implies continuously valid inputs Skew inevitably causes inconsistency at the inputs and hence invalid dynamic states A B C F 1 Lecture "Advanced Digital Design" A © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna Resume 3 In practice temporal relations DO matter for a design. Boolean logic is not capable of expressing them. We need other means of introducing the missing information. This is exactly the purpose of a design style. Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

The Fundamental Problem of Digital Design - a communication problem

© A. Steininger & M. Delvai / TU Vienna What we actually need When can SNK use its input? When it is valid and consistent f(x) SRC SNK When can SRC apply the next input? When SNK has consumed the previous one Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna Terminology consistent DW: all bits belong to the same context valid signal: result of function applied to consistent DW Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna Conclusion The purpose of a design style is to provide information for flow control. Boolean Logic alone cannot provide this information. Severe technological problems force us to question the current (synchronous) design practice. We shall focus on that. Alternatives must be evaluated very critically with respect to improvements concerning power, area, robustness, ease of composition, testability and performance. Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna Our Options We must only use consistent input vectors How can we tell an input vector is consistent? (1) use TIME to mark consistent phases synchronous approach asynchronous/bounded delay (2) use CODING to add information asynchronous/delay insensitive Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

© A. Steininger & M. Delvai / TU Vienna Timed Comm. Model Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna