Direct Mapping.

Slides:

Advertisements

Similar presentations

Cache Memory Exercises. Questions I Given: –memory is little-endian and byte addressable; memory size; –number of cache blocks, size of cache block –An.

Advertisements

Computer Organization and Architecture

Homework 2 Review Cornell CS Calling Conventions int gcd(int x, int y) { int t, a = x, b = y; while(b != 0) { t = b; b = mod(a, b); a = t; } return.

The Lord of the Cache Project 3. Caches Three common cache designs: Direct-Mapped store in exactly one cache line Fully Associative store in any cache.

6/12/2015Page 1 Exploiting Memory Hierarchy Chapter 7 B.Ramamurthy.

How caches take advantage of Temporal locality

Memory Hierarchies Exercises [ ] Describe the general characteristics of a program that would exhibit very little spatial or temporal locality with.

Characteristics of Computer Memory

Caches The principle that states that if data is used, its neighbor will likely be used soon.

Characteristics Location Capacity Unit of transfer Access method Performance Physical type Physical characteristics Organisation.

1 Answers to Test 1, Question 1 The functions determines if a positive number is prime. It does this by checking if the number is lower than 4, if so it.

Direct Map Cache Tracing Exercise. Exercise #1: Setup Information CS2100 Cache I 2 Memory 4GB Memory Address 310N-1N Block Number Offset 1 Block = 8 bytes.

CDA 3103 Computer Organization Review Instructor: Hao Zheng Dept. Comp. Sci & Eng. USF.

CSCE 212 Quiz 11 – 4/13/11 Given a direct-mapped cache with 8 one-word blocks and the following 32-bit memory address references: 1 2, ,

Characteristics of Computer Memory

COEN 180 Main Memory Cache Architectures. Basics Speed difference between cache and memory is small. Therefore:  Cache algorithms need to be implemented.

Faculty of Information Technology Department of Computer Science Computer Organization and Assembly Language Chapter 4 Cache Memory.

CMPE 421 Parallel Computer Architecture

Lecture Objectives: 1)Define set associative cache and fully associative cache. 2)Compare and contrast the performance of set associative caches, direct.

Cache Control and Cache Coherence Protocols How to Manage State of Cache How to Keep Processors Reading the Correct Information.

1 CMPE 421 Advanced Computer Architecture Accessing a Cache PART1.

Computer Architecture Lecture 26 Fasih ur Rehman.

ACOE2011 Cache memory Homework – Q1 A computer has a 32 bit address and a 64 bit data bus with address resolution to the byte level. The computer is using.

2007 Sept. 14SYSC 2001* - Fall SYSC2001-Ch4.ppt1 Chapter 4 Cache Memory 4.1 Memory system 4.2 Cache principles 4.3 Cache design 4.4 Examples.

CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.

Memory Hierarchy. Hierarchy List Registers L1 Cache L2 Cache Main memory Disk cache Disk Optical Tape.

1 Chapter Seven. 2 Users want large and fast memories! SRAM access times are ns at cost of $100 to $250 per Mbyte. DRAM access times are ns.

DECStation 3100 Block Instruction Data Effective Program Size Miss Rate Miss Rate Miss Rate 1 6.1% 2.1% 5.4% 4 2.0% 1.7% 1.9% 1 1.2% 1.3% 1.2% 4 0.3%

1 Chapter Seven. 2 Users want large and fast memories! SRAM access times are ns at cost of $100 to $250 per Mbyte. DRAM access times are ns.

Additional Slides By Professor Mary Jane Irwin Pennsylvania State University Group 1.

Cache Operation.

Cache Small amount of fast memory Sits between normal main memory and CPU May be located on CPU chip or module.

CSE 351 Caches. Section Feedback Before we begin, we’d like to get some feedback about section If you could answer the following questions on the provided.

Memory Hierarchy— Five Ways to Reduce Miss Penalty.

Memory Hierarchy and Cache Design (3). Reducing Cache Miss Penalty 1. Giving priority to read misses over writes 2. Sub-block placement for reduced miss.

نظام المحاضرات الالكترونينظام المحاضرات الالكتروني Cache Memory.

Characteristics Location Capacity Unit of transfer Access method Performance Physical type Physical characteristics Organisation.

Associative Mapping A main memory block can load into any line of cache Memory address is interpreted as tag and word Tag uniquely identifies block of.

CSCI206 - Computer Organization & Programming

DREAM TEAM 2 Roto, Holiano, Chaka

William Stallings Computer Organization and Architecture 7th Edition

Tutorial Nine Cache CompSci Semester One 2016.

CS2100 Computer Organization

Memory Hierarchy Virtual Memory, Address Translation

Consider a Direct Mapped Cache with 4 word blocks

William Stallings Computer Organization and Architecture 7th Edition

Exploiting Memory Hierarchy Chapter 7

BIC 10503: COMPUTER ARCHITECTURE

CSCI206 - Computer Organization & Programming

FIGURE 12-1 Memory Hierarchy

Interconnect with Cache Coherency Manager

Lecture 22: Cache Hierarchies, Memory

Help! How does cache work?

Module IV Memory Organization.

Chapter 6 Memory System Design

Chapter 6 Memory Linda Null, Julia Lobur.

Basic Cache Operation Prof. Eric Rotenberg

Overview Problem Solution CPU vs Memory performance imbalance

Presentation transcript:

Direct Mapping

Direct Mapping Address Structure Tag s-r Line or Slot r Word w 14 2 8 24 bit address 2 bit word identifier (4 byte block) 22 bit block identifier 8 bit tag (=22-14) 14 bit slot or line No two blocks in the same line have the same Tag field Check contents of cache by finding line and checking Tag

Direct Mapping Formula i = j modulo m where i = cache line number j = main memory block number m = number of lines in the cache

Direct Mapping Summary

Associative Mapping

Associative Mapping Address Structure Word 2 bit Tag 22 bit Example:

Associative Mapping Summary

Set Associative Mapping

Set Associative Mapping Address Structure s - d Tag 9 bit d Set 13 bit Word 2 bit Use set field to determine cache set to look in Compare tag field to see if we have a hit

Set Associative Mapping Formula

Set Associative Mapping Summary Address length = (s + w) bits Number of addressable units = 2s+w words or bytes Block size = line size = 2w words or bytes Number of blocks in main memory = 2s+w/2w=2s Number of lines in set = k Number of sets = v = 2d Number of lines in cache = m=kv = k * 2d Size of cache = k * 2d+w words or bytes Size of tag = (s – d) bits