ECE 3430 – Intro to Microcomputer Systems ECE 3430 – Introduction to Microcomputer Systems University of Colorado at Colorado Springs Lecture #13 Agenda Today: Interrupts (Internal and External) Interrupt Service Routines (ISRs) Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2014

ECE 3430 – Intro to Microcomputer Systems Interrupts Interrupt Request (IRQ) - An event that stops normal program operation - Performs a service routine (executes specific code) - Returns the program to normal operation MSP430 - The MSP430 provides a specific set of interrupts - See the full datasheet for details Why have interrupts? 1) I/O handling – The CPU can execute the main program and then react to incoming data—rather than periodically testing for data (polling). Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2014

ECE 3430 – Intro to Microcomputer Systems Interrupts 2) Software Errors – A program encounters errors for many different reasons (HW, SW). We need to handle these gracefully instead of letting the program run amuck. 3) Perform Periodic Tasks - Anything that needs to occur at a pre-defined frequency is done with an interrupt. This ensures more precise timing. (ex, update a clock each second) 4) Multitasking - We can time-share between multiple programs by using an interrupt to indicate when to switch to the next program. 5) Waking the CPU from a Sleep State - In low-power design, the uC will sleep when there is nothing to do and wake up in response to events. Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2014

ECE 3430 – Intro to Microcomputer Systems Interrupts Interrupts can be classified as: Externally or Internally-Generated Maskable or Non-Maskable Edge or Level-Sensitive (Applies to Externally-Generated Interrupts) External interrupts: In this course are interrupts generated by devices external from the MSP430 microcontroller: All of the ports pins, NMI, and RST input pins. External hardware asserts one of these inputs to interrupt the CPU. Internal interrupts: In this course are interrupts generated by on-chip peripheral devices: watchdog timer, flash memory access violation, timer, et cetera. On-chip peripheral devices can interrupt the CPU. Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2014

ECE 3430 – Intro to Microcomputer Systems Interrupts Maskable Interrupts - Some interrupts can be ignored: “Maskable Interrupts” - Some interrupts CANNOT: “Non-Maskable Interrupts” (NMI) Notation (IRQ = Interrupt Request) Pending - When an interrupt occurs, but has not been serviced by the CPU. Service - Executing the code to perform what the interrupt wants done. Service Routine - The code that executes when the interrupt is serviced. (ISR = Interrupt Service Routine) Priority - Interrupts can occur simultaneously. - Some interrupts are more important than others (i.e., a fire alarm). - Higher priority interrupts are chosen over lower priority interrupts. Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2014

ECE 3430 – Intro to Microcomputer Systems Interrupts MSP430 CPU Operation When an Interrupt Occurs 1) Complete the currently-executing instruction. 2) Save program counter on stack (marks return address). 3) Save CPU status on stack (SR). 4) Clear bits in status register (SR)—wakes CPU if necessary and prevents further interrupts. 5) Identify the cause of the interrupt. 6) Retrieve the starting address of the ISR (where in memory the code resides). 7) Adjust PC and execute the interrupt service routine (ISR). 8) Restore the CPU registers/status and program counter from stack. 9) Adjust PC and resume interrupted program. Interrupt Vector - The starting address of the ISR - An ISR is written very similar to a subroutine. The starting address is given a label: Ex) Isr1: <code…> 0xC000 Main 0xC??? Sub1 0xC??? Sub2 0xF??? Isr1 Interrupt Vector Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2014

ECE 3430 – Intro to Microcomputer Systems Interrupts Interrupt Vector Table - Predefined address that hold the interrupt vectors (ISR addresses). - Each MSP430 interrupt (internal and external) has a spot in the interrupt vector table. Ex) The reset is an interrupt. We already know how to initialize its interrupt vector: ORG 0xFFFE Reset: DW 0xC000 “Interrupt Vector” = 0xC000 “Interrupt Vector Table address” = 0xFFFE - When the reset interrupt occurs, the PC is loaded with the data that resides in 0xFFFE and 0xFFFF. - The MSP430 knows to look at this address. - The PC is loaded with this value and code is executed beginning there. - In our case, we use 0xC000 (beginning of the Flash memory for G2553 part). - The same process is used for other IRQs. - When interrupt occurs, PC = Interrupt Vector. 0xFFFE 0x00 0xFFFF 0xC0 Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2014

Interrupts This is not an exhaustive list. Interrupt Vector Table - The MSP430 has 32, 16-bit vector table entries. - The vector table ranges from 0xFFC0-0xFFFF. - 0xFFC0 is the lowest priority and 0xFFFE is the highest priority. - Note that this memory range maps to the non-volatile Flash memory. - The meaning of each vector table entry is somewhat device-specific. MSP430G2553 Vector Table (from device-specific datasheet) - 0xFFC0-0xFFDE: Not used and can be used for regular program code. - 0xFFE4: Port 1 interrupts. - 0xFFEA: A/D converter. - 0xFFF0 and 0xFFF2: Timers. - 0xFFF4: Watchdog timer. - 0xFFFC: NMI, oscillator fault, flash memory access violation. - 0xFFFE: Power up, external reset, flash key violation, PC out-of-range. This is not an exhaustive list. Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2014

ECE 3430 – Intro to Microcomputer Systems Interrupts Interrupt Programming (1 of 3) There are 3 steps that must be done to use interrupts: 1) Initialize the “Interrupt Vector Table” Ex) ORG 0xFFFE DW 0xC000 ORG 0xFFE4 DW P1_ISR NOTE: Generally speaking, it is good practice to initialize all vector table locations even if you aren’t explicitly using them. This way the behavior is predictable if an interrupt occurs that you weren’t planning to handle. Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2014

ECE 3430 – Intro to Microcomputer Systems Interrupts Interrupt Programming (2 of 3) 2) Write Service Routine - This is the same as writing a subroutine, EXCEPT instead of RET we use RETI “Return from Interrupt”. We still need to use the do-no-damage paradigm because the system does not do this for us. We need to do push and pull operations to preserve the caller’s programming model registers! Ex) ORG 0xC000 MAIN: … … SUB1: … ret ISR1: … reti NOTE: It is perfectly acceptable (although typically not desirable) for an interrupt service routine to call subroutines. P1_IRQ: call #SUB1 Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2014

ECE 3430 – Intro to Microcomputer Systems Interrupts Interrupt Programming (3 of 3) 3) Enable Interrupts There are two types of flags that turn on/off interrupts: Global = Will enable multiple interrupts (GIE flag in the status register) Local = Will enable individual interrupts. Set bits in peripheral module control registers or in special function registers. The control registers are mapped to memory locations 0x0000-0x01FF in the MSP430. - Some interrupts have global and local enable bits. - Some interrupts have only a global enable bit. - Some interrupts are always enabled. (See the MSP430 datasheets for more information about any specific interrupt source) Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2014

ECE 3430 – Intro to Microcomputer Systems Interrupts The Stack and Interrupts - When an interrupt occurs, the status of the CPU is stored on the stack. - The stack must be initialized prior to the first interrupt or you will have major problems. - 4 bytes (2 words) are pushed onto the stack automatically by the hardware when an IRQ occurs. - For this reason, interrupts have latency associated with them. - The RETI instruction will pull all of this info off of the stack and return the program to normal operation. Note that R4-R15 are not automatically pushed so you need to if you use them! 0x03FC 0x03FD 0x03FE 0x03FF SP SR (low) SR (high) PC (low) PC (high) Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2014

ECE 3430 – Intro to Microcomputer Systems Interrupts Maskable Interrupts - The “GIE” flag in the SR is a global enable for a group of interrupts called maskable interrupts. - The “GIE” bit will enable/disable “global interrupts” for this group. GIE = 1, ENABLE global maskable interrupts Use EINT GIE = 0, DISABLE global maskable interrupts Use DINT Non-Maskable Interrupts (NMI) - Interrupts that are not classified as maskable are called non-maskable interrupts. - Generally speaking, these are always enabled and cannot be ignored. - Examples include reset conditions and the NMI external interrupt pin. Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2014

ECE 3430 – Intro to Microcomputer Systems Interrupts See the MSP430 device-specific datasheet for details on the device-specific interrupt sources, flags, and vector addresses. Links to the datasheets are available on the course web page. Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2014

ECE 3430 – Intro to Microcomputer Systems Interrupts When an IRQ interrupt occurs, the GIE bit in the SR is cleared to inhibit further interrupts. The SR interrupt flag modification occurs after the status register is pushed to the stack. When the RETI instruction executes, the contents are pulled from the stack and the interrupt flag is restored to its previous state. If the CPU woke from a low-power state in response to an interrupt, the RETI Instruction will restore the low-power state with the ISR is finished. Any non-maskable interrupt with can always interrupt the CPU—even if a maskable ISR is currently executing. Unless the programmer explicitly sets the GIE bit after entering an ISR (using the EINT instruction), no maskable interrupts (even at a higher priority level) can interrupt the ISR in progress. When the ISR completes, the highest pending interrupt will get the attention of the CPU. Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2014

ECE 3430 – Intro to Microcomputer Systems Interrupts Interrupt service routines (ISR) should do the minimum amount of work required to eliminate the interrupt. Interrupt service routines should be short, sweet, and to the point! GET IN CLEAR INTERRUPT GET OUT Ex) Assume an external device asserts an interrupt line to tell uC it has some data for it. The ISR should interrogate the device to determine what it needs to do to make the device stop interrupting. Generally, the uC would perform a set of operations on the device. The device releases the interrupt line in response to these operations. If the uC needs to do more work in response to the interrupt, that work should be done outside of the ISR. Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2014

ECE 3430 – Intro to Microcomputer Systems Interrupts Most of the productive work a uC or uP does should be done outside of interrupt service routines. Spending too much time in interrupt service routines can severely hurt the system performance! When servicing an interrupt generated by an on-chip peripheral device, data is typically written to control registers or special function registers (0x0000-0x01FF) to cause the on-chip peripheral device to de-assert the interrupt. Extended ISR responsibilities are carried out by a deferred procedure (perhaps the main loop). Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2014

ECE 3430 – Intro to Microcomputer Systems Interrupts External interrupts can be edge sensitive or level sensitive. Edge sensitive interrupts trigger on a rising or falling edge of the interrupt pin. When the ISR is complete, another interrupt does not fire until another edge is detected. Level sensitive interrupts trigger on an active logic level. When the ISR is complete, another interrupt will immediately fire if the interrupt line is still asserted. MSP430 specific: RST: Level sensitive NMI: Edge sensitive (programmable edge) Port 1 and Port 2: Edge sensitive (programmable edge). RST is active-low. Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2014

ECE 3430 – Intro to Microcomputer Systems Interrupts NMI external interrupt: The WDTCTL control register contains bits to configure this. The WDTNMI, WDTNMIES bits in the WDTCTL register control the setup… WDTNMI = 0  RST/NMI pin assumes RST role. WDTNMI = 1  RST/NMI pin assumes NMI role. WDTNMIES = 0  NMI on rising edge WDTNMIES = 1  NMI on falling edge To enable: Set NMIIE bit in the IE1 special function register (bis.b #NMIIE,IE1). On interrupt (when interrupt is pending that is): The NMIIFG flag in the IFG1 register is set. The NMI vector is consulted. Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2014

ECE 3430 – Intro to Microcomputer Systems Interrupts Port 1 and Port 2 external interrupt: All port 1 pins (interrupt sources) share a common interrupt vector. All port 2 pins (interrupt sources) share a common different interrupt vector. To distinguish from the 8 potential sources, the PxIFG register is consulted. Each pin has a bit in this register. Priority can be assigned by software. Because port interrupts are classified as maskable, the GIE bit in the status register must be set as well. The PxIES register allows you to set the edge sensitivity for each pin independently. To enable: The interrupt capability of each I/O pin can be controlled independently through the PxIE register (bit 7-0). The GIE bit in the status register must be set also. On interrupt (when interrupt is pending that is): The appropriate bit (7-0) in the PxIFG register is set. The port vector is consulted. Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2014

ECE 3430 – Intro to Microcomputer Systems Interrupts Port 1 and Port 2 external interrupt: In the ISR, the appropriate flag in the PxIFG register must be cleared! If this is not done, the ISR will immediately restart after the RETI instruction. Software can also set the flags to produce a “software interrupt”. Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2014

Low Power Modes Active mode (AM) – All clocks are active Low-power mode 0 (LPM0) – CPU and MCLK is disabled Low-power mode 1 (LPM1) – LPM0 + DCO's dc generator is disabled if DCO not used in active mode Low-power mode 2 (LPM2) – LPM1 + SMCLK is disabled – DCO's dc generator remains enabled Low-power mode 3 (LPM3) – LPM2 + DCO's dc generator is disabled Low-power mode 4 (LPM4) – LPM3 + ACLK and crystal oscillator is disabled Less Power, Longer Wakeup Time Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2014

ECE 3430 – Intro to Microcomputer Systems Low Power Modes Mode controlled by the SCG1, SCG0, OSCOFF, and CPUOFF flags in the status register (SR/R2). Active mode (AM) – All above control bits 0 (default). Low-power mode 0 (LPM0) – CPUOFF = 1  bis #LPM0, SR Low-power mode 1 (LPM1) – CPUOFF = 1, SCG0 = 1  bis #LPM1, SR Low-power mode 2 (LPM2) – CPUOFF = 1, SCG1 = 1  bis #LPM2, SR Low-power mode 3 (LPM3) – CPUOFF = 1, SCG1 = 1, SCG0 = 1  bis #LPM3, SR Low-power mode 4 (LPM4) – CPUOFF = 1, SCG1 = 1, SCG0 = 1, OSCOFF = 1  bis #LPM4, SR Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2014

Port 1 Interrupt Example Ex) Write an ISR that toggles P1.4 (output) when P1.0 (input) sees a rising edge (0 to 1 transition): ORG 0xFFE4 ; setup interrupt vector table entry for P1 external interrupts DW P1_Isr ORG 0xFFFE ; setup interrupt vector table for external RESET DW Start ORG 0xC000 Start: mov #0x0400,SP ; set stack pointer (512B RAM device) mov #WDTPW+WDTHOLD, &WDTCTL ; stop watchdog timer mov.b #11111110b, &P1DIR ; make P1.0 an input (assume P1.7-P1.1 are ; outputs or unused) clr.b &P1IES ; rising edge bis.b #00000001b, &P1IE ; turn on local interrupt enable eint ; enable global, maskable interrupts (set GIE bit) Main_Lp: … jmp Main_Lp ; repeat a main loop <or> bis #LPM4,SR ; fall asleep until transition P1_Isr: xor.b #00010000b, &P1OUT ; flip only P1.4 to opposite state (don’t change other bits) bic.b #00000001b, &P1IFG ; clear flag that caused interrupt reti ; go back to Main_Lp processing Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2014

ECE 3430 – Intro to Microcomputer Systems Remember (Important) All interrupts are assigned a priority. If multiple interrupts occur simultaneously, the highest priority ISR is chosen first and so on down to the lowest priority. A periodically-occurring high-priority interrupt can starve lower-priority interrupts (and the main loop) from receiving CPU time! All non-maskable interrupts will always interrupt maskable interrupts. Maskable interrupts can only interrupt other maskable interrupts if an interrupt with a strictly higher priority level interrupts and the programmer set the GIE flag in the SR when entering the lower-priority ISR. Otherwise higher-priority maskable interrupts have to wait on the lower-priority to finish first! Lecture #13 ECE 3430 – Intro to Microcomputer Systems Fall 2014