1 Overview of Microprocessors A. Parveen

2 Lecture overview Introduction to microprocessors Instruction set architecture Typical commercial microprocessors

3 Microprocessors A microprocessor is a CPU on a single chip. If a microprocessor, its associated support circuitry, memory and peripheral I/O components are implemented on a single chip, it is a microcontroller. We use AVR microcontroller as the example in our course study

Week34 Microprocessor types Microprocessors can be characterized based on the word size 8 bit, 16 bit, 32 bit, etc. processors Instruction set structure RISC (Reduced Instruction Set Computer), CISC (Complex Instruction Set Computer) Functions General purpose, special purpose such image processing, floating point

Week35 Typical microprocessors Most commonly used 68K Motorola x86 Intel IA-64 Intel MIPS Microprocessor without interlocked pipeline stages ARM Advanced RISC Machine PowerPC Apple-IBM-Motorola alliance Atmel AVR A brief summary will be given later

Week36 Microprocessor applications A microprocessor application system can be abstracted in a three-level architecture ISA is the interface between hardware and software Software Hardware C program ISA level ISA program executed by hardware FORTRAN 90 program FORTRAN 90 program compiled to ISA program C program compiled to ISA program

Week37 ISA Stands for Instruction Set Architecture Provides functional specifications for software programmers to use/program hardware to perform certain tasks Provides the functional requirements for hardware designers so that their hardware design (called micro-architectures) can execute software programs.

Week38 What makes an ISA ISA specifies all aspects of a computer architecture visible to a programmer Basic Instructions  Instruction format  Addressing modes Native data types Registers Memory models advanced Interrupt handling  To be covered in the later lectures

Week39 Instructions This is the key part of an ISA specifies the basic operations available to a programmer Example: Arithmetic instructions Instruction set is machine oriented Different machine, different instruction set For example  68K has more comprehensive instruction set than ARM

Week310 Instructions (cont.) Instruction set is machine oriented Same operation, could be written differently in different machine AVR  Addition: add r2, r1 ;r2  r2+r1  Branching: breq 6;branch if equal condition is true  Load: ldi r30, $F0;r30  Mem[F0] 68K:  Addition: add d1,d2;d2  d2+d1  Branching: breq 6;branch if equal condition is true  Load: mov #1234, D3;d3  1234

Week311 Instructions (cont.) Instructions can be written in two languages Machine language made of binary digits Used by machines Assembly language a textual representation of machine language Easier to understand than machine language Used by human beings

Week312 Machine code vs. assembly code There is a one-to-one mapping between the machine code and assembly code Example (Atmel AVR instruction): For increment register 16: (machine code) inc r16 (assembly language) Assembly language also includes directives Instructions to the assembler Example:.def temp = r16.include “mega64def.inc”

Week313 Data types The basic capability of using different classes of values. Typical data types Numbers Integers of different lengths (8, 16, 32, 64 bits)  Possibly signed or unsigned  Commonly available Floating point numbers, e.g. 32 bits (single precision) or 64 bits (double precision)  Available in some processors such as PowerPC BCD (binary coded decimal) numbers  Available in some processors, such as 68K Non-numeric Boolean Characters

Week314 Data types (cont.) Different machines support different data types in hardware e.g. Pentium II: e.g. Atmel AVR: Data Type8 bits16 bits32 bits64 bits128 bits Signed integer Unsigned integer BCD integer Floating point Data Type8 bits16 bits32 bits64 bits128 bits Signed integer Partial Unsigned integer Partial BCD integer Floating point

Week315 Registers Two types General purpose Special purpose Used for special functions e.g.  Program Counter (PC)  Status Register  Stack pointer (SP)  Input/Output Registers Stack pointer and Input/Output Registers will be discussed in detail later.

Week316 General Purpose Registers A set of registers in the machine Used for storing temporary data/results For example In (68K) instruction add d3, d5, operands are stored in general registers d3 and d5, and the result are stored in d5. Can be structured differently in different machines For example Separated general purpose registers for data and address  68K Different numbers registers and different size of each registers  bit in MIPS  bit in ARM

Week317 Program counter Special register For storing memory address of currently executed instruction Can be of different size E.g. 16 bit, 32 bit Can be auto-incremented By the instruction word size Gives rise the name “counter”

Week318 Status register Contains a number of bits with each bit associated with CPU operations Typical status bits V: Overflow C: Carry Z: Zero N: Negative Used for controlling program execution flow

Week319 Memory models Data processed by CPU is usually large and cannot be held in the registers at the same time. Both data and program code need to be stored in memory. Memory model is related to how memory is used to store data Issues Addressable unit size Address spaces Endianness Alignment

Week320 Addressable unit size Memory has units, each of which has an address Most common unit size is 8 bits (1 byte) Modern processors have multiple-byte unit For example: 32-bit instruction memory in MIPs 16-bit Instruction memory in AVR

Week321 Address spaces The range of addresses a processor can access. The address space can be one or more than one in a processor. For example Princeton architecture or Von Neumann architecture  A single linear address space for both instructions and data memory Harvard architecture  Separate address spaces for instructions and data memories

Week322 Address spaces (cont.) Address space is not necessarily just for memories E.g, all general purpose registers and I/O registers can be accessed through memory addresses in AVR Address space is limited by the width of the address bus. The bus width: the number of bits the address is represented

Week323 Endianness Memory objects Memory objects are basic entities that can be accessed as a function of the address and the length E.g. bytes, words, longwords For large objects (>byte), there are two ordering conventions Little endian – little end (least significant byte) stored first (at lowest address) Intel microprocessors (Pentium etc) Big endian – big end stored first SPARC, Motorola microprocessors

Week324 Endianness (cont.) Most CPUs produced since ~1992 are “bi-endian” (support both) some switchable at boot time others at run time (i.e. can change dynamically)

Week325 Big Endian & Little Endian Example: 0x —a long word of 4 bytes. It is stored in the memory at address 0x big endian: little endian: Address data 0x x x x Address data 0x x x x

Week326 Alignment Often multiple bytes can be fetched from memory Alignment specifies how the (beginning) address of a multiple-byte data is determined. data must be aligned in some way. For example 4-byte words starting at addresses 0,4,8, … 8-byte words starting at addresses 0, 8, 16, … Alignment makes memory data accessing more efficient

Week327 Example A hardware design that has data fetched from memory every 4 bytes Fetching an unaligned data (as shown) means to access memory twice.

Week328 Instruction format Is a definition how instructions are represented in binary code Instructions typically consist of Opcode (Operation Code) defines the operation (e.g. addition) Operands what’s being operated on Instructions typically have 0, 1, 2 or 3 operands

Week329 Instruction format examples OpCode Opd1Opd2Opd1 Opd Opd2Opd3

Week330 Example (AVR instruction) Subtraction with carry Syntax: sbc Rd, Rr Operation: Rd ← Rd – Rr – C Rd: Destination register. 0  d  31 Rr: Source register. 0  r  31, C: Carry Instruction format OpCode uses 6 bits (bit 9 to bit 15). Two operands share the remaining 10 bits r dr r d d 015

Week331 Instruction lengths The number of bits an instruction has For some machines – instructions all have the same length E.g. MIPS machines For other machines – instructions can have different lengths E.g. M68K machine

Week332 Instruction encoding Operation Encoding 2 n operations needs at least n bits Operand Encoding Depends on the addressing modes and access space. For example: An operand in direct register addressing mode requires at most 3 bits if the the number of registers it can be stored is 8. With a fixed instruction length, more encoding of operations means less available bits for encoding operands Tradeoffs should be concerned

Week333 Example 1 A machine has: 16 bit instructions 16 registers (i.e. 4-bit register addresses) Instructions could be formatted like this: Maximally 16 operations can be defined. But what if we need more instructions and some instructions only operate on 0, 1 or 2 registers? OpCode Operand1 Operand2 Operand3

Week334 Example 2 For a 16 bit instruction machine with 16 registers, design OpCodes that allow for 14 3-operand instructions 30 2-operand instructions 30 1-operand instructions 32 0-operand instructions

Week335 Addressing modes Instructions need to specify where to get operands from Some possibilities Values are in the instruction Values are in the register Register number is in the instruction Values are in memory address is in instruction address is in a register  register number is in the instruction address is register value plus some offset  register number is in the instruction  offset is in the instruction (or in a register) These ways of specifying the operand locations are called addressing modes

Week336 Immediate Addressing The operand is from the instruction itself I.e the operand is immediately available from the instruction For example, in 68K Perform d7  99 + d7; value 99 comes from the instruction d7 is a register addw #99, d7

Week337 Register Direct Addressing Data from a register and the register number is directly given by the instruction For example, in 68K Perform d7  d7 + d0; add value in d0 to value in d7 and store result to d7 d0 and d7 are registers addw d0,d7

Week338 Memory direct addressing The data is from memory, the memory address is directly given by the instruction We use notion: (addr) to represent memory value with a given address, addr For example, in 68K Perform d7  d7 + (0x123A); add value in memory location 0x123A to register d7 addw 0x123A, d7

Week339 Memory Register Indirect Addressing The data is from memory, the memory address is given by a register and the register number is directly given by the instruction For example, in 68K Perform d7  d7 + (a0); add value in memory with the address stored in register a0, to register d7 For example, if a0 = 100 and (100) = 123, then this adds 123 to d7 addw (a0),d7

Week340 Memory Register Indirect Auto-increment The data is from memory, the memory address is given by a register, which is directly given by the instruction; and the value of the register is automatically increased – to point to the next memory object. Think about i++ in C For example, in 68K d7  d7 + (a0); a0  a0 + 2 addw (a0)+,d7

Week341 Memory Register Indirect Auto-decrement The data is from memory, the memory address is given by a register and the register number is directly given by the instruction; but the value of the register is automatically decreased before such an operation. Think --i in C For example, in 68K a0  a0 –2; d7  d7 + (a0); addw -(a0),d7

Week342 Memory Register Indirect with Displacement Data is from the memory with the address given by the register plus a constant Used in the access of a member in a data structure For example, in 68K d7  (a0+8) +d7 addw d7

Week343 Address Register Indirect with Index and displacement The address of the data is sum of the initial address and the index address as compared to the initial address plus a constant Used in accessing element of an array For example, in 68K d7  (a0 + d3+8) With a0 as an initial address and d3 as an index dynamically pointing to different elements, plus a constant for a certain member in an array element. addw d7

Week344 RISC RICS stands for reduced instruction set computer Smaller and simpler set of instructions Smaller: small number of instructions in the instruction set Simpler: instruction encoding is simple  Such as fixed instruction length All instructions take about the same amount of time to execute

Week345 CISC CISC stands for complex instruction set computer Each instructions can execute several low-level operations Such operations of load memory, arithmetic and store memory in one instructions Required complicated hardware support All instructions take different amount of time to execute

Week346 Recall: Typical processors Most commonly implemented in hardware 68K Motorola x86 Intel IA-64 Intel MIPS Microprocessor without interlocked pipeline stages ARM Advanced RISC Machine PowerPC Apple-IBM-Motorola alliance Atmel AVR

Week347 X86 CISC architecture 16 bit  32-bit  64-bit Words are stored in the little endian order Allow unaligned memory access. Current x86-processors employs a few “extra” decoding steps to (during execution) split (most) x86 instructions into smaller pieces (micro-instructions) which are then readily executed by a RISC-like micro-architecture. Application areas (dominant) Desktop, portable computer, small servers

Week348 68K CISC processor Early generation, hybrid 8/16/32 bit chip (8-bit bus) Late generation, fully 32-bit Separate data registers and address registers Big endian Area applications Early used in for calculators, control systems, desktop computers Later used in microcontroller/embedded microprocessors.

Week349 MIPS RISC processor A large family designs with different configurations Deep pipeline (>=5 stages) With additional features Clean instruction set Could be booted either big-endian or little-endian Many application areas, including embedded systems The design of the MIPS CPU family, together with SPARC, another early RISC architecture, greatly influenced later RISC designs

Week350 ARM 32-bit RISC processor Three-address architecture No support for misaligned memory accesses 16 x 32 bit register file Fixed opcode width of 32 bit to ease decoding and pipelining, at the cost of decreased code density Mostly single-cycle execution With additional features Conditional execution of most instructions  reducing branch overhead and compensating for the lack of a branch predictor  Powerful indexed addressing modes Power saving

Week351 PowerPC Superscalar RISC 32-bit, 64-bit implementation With both big-endian and little endian modes, can switch from one mode to the other at run- time. Intended for high performance PC, for high- end machines

Week352 Reading Material Chap.2 in Microcontrollers and Microcomputers.

Week353 Questions 1. Given an address bus width in a processor as 16-bit, determine the maximal address space. 2. Assume a memory address is 0xFFFF, how many locations this address can represent if the related computer is? I) a Harvard machine II) a Von Neumann machine