Yufei Wu, Jesús A. del Alamo Anomalous Source-side Degradation of InAlN/GaN HEMTs under ON-state Stress Yufei Wu, Jesús A. del Alamo Microsystems Technology Laboratories, Massachusetts Institute of Technology October 04, 2016 C1.1: RF/mm Wave Devices I: Electronic Devices for RF Applications and Late News Session Chairs: Andrea Corrion Tuesday Morning, October 4, 2016 Room: Narcissus/Orange Blossom 9:30 AM C1.1.04 Anomalous Source-Side Degradation of InAlN/GaN HEMTs under ON State Stress Yufei Wu and Jesus del Alamo; EECS, MIT, Cambridge, Massachusetts, United States. Sponsor: NRO Contract No. DII NRO000-13C0309 Collaborator: Jose Jimenez (Qorvo)

Outline Motivation Source-side degradation under ON-stress Gate leakage current and its temperature dependence Positive gate stress Conclusions

Motivation: InAlN as barrier   Al0.2Ga0.8N/GaN ln0.17Al0.83N/GaN Δ P0 (ecm-2) 6.5 x 1012 2.7 x 1013 Ppiezo (ecm-2) 5.3 x 1012 Ptotal (ecm-2) 1.2 x 1013 In0.17Al0.83N [J. Kuzmik, EDL 2001] Compared with the conventional AlGaN/GaN EHMTs, the use of an InAlN barrier yields a higher spontaneous polarization-induced charge at the barrier/GaN interface for the same layer thickness, . This enables aggressive barrier thickness scaling and therefore greater gate length scaling. As a result, InAlN/GaN HEMTs are extremely promising for very high-frequency applications. In addition, with an Indium mole fraction of 0.17, InAlN can be grown lattice matched to GaN. And as a result, this new material system has the potential of showing better reliability. High spontaneous polarization in InAlN  high 2DEG density InAlN thickness scaling  gate length scaling  W- and V-band applications [M. A. Laurent, JAP 2014] In0.17Al0.83N lattice matched to GaN  Potentially better reliability!

Motivation: InAlN as barrier InAlN/GaN HEMTs W-band E-mode Four gate geometries: Wg = 8 X 25 µm Wg = 8 X 50 µm Wg = 2 X 25 µm Wg = 2 X 50 µm Thermal models available Mention: This would allow us to estimate the junction temperature. [Saunier, CSICS 2014]

High-VDS-high-ID stress Stress and characterization conditions: VDS,stress = 25 V, IDstress = 400 mA/mm (VG ~ 1.5 V), 5 mins, RT (Tj ~ 136 °C) Characterization: @ 25 °C after thermal detrapping The operating voltage for the device is ~ 15V Permanent degradation: Significant IDmax degradation ΔVT > 0 Significant IDoff degradation

High-VD-high-ID stress After thermal detrapping, gate current degradation: IG, IS after stress Large increase in IG after stress After stress: IG = IS >> ID in forward and reverse bias Source-side damage unexpected! Uncommon but previously observed in AlGaN/GaN HEMTs [J. Joh, IEDM 2010] ID after stress IG before stress IS before stress ID before stress VDS = 0 V

Temperature dependence of IG and ID T-dependence of ID: T-dependence of IG: After stress After stress Before stress Before stress VDS=0 VDS=0 Before stress: For moderate VGS, negative T coefficient  thermionic emission limited current IS behaves similar to IG After stress: Significantly reduced T dependence for IG and IS ID less affected  degradation on source side

HRTEM of a virgin device drain side Virgin device source side Gate metal Gate metal passivation passivation InAlN InAlN AlN AlN GaN GaN Residual oxide? Gate recessed to the AlN interlayer

HRTEM of stressed device drain side Stressed device source side Gate metal Gate metal passivation passivation InAlN InAlN AlN AlN GaN GaN Disordered region in GaN channel at gate edge on source side

Hypothesis for Damage High VDS,stress + high IDstress high IGstress too  high IGS  high Tj  high electric field across AlN barrier on source side Conditions favor defect formation in AlN barrier on source side  IGS↑ Also, gate sinking  ΔVT>0

Positive VG step-stress-recovery experiment Stress and characterization conditions: VGS,stress = 0 - 2.5 V, VDS,stress = 0 V, step = 0.1 V, RT (Tj ~ 48 °C) Characterization: @ 25 °C after thermal detrapping Justify the reason for this experiment Previous experiment shows that forward VG together with high IGstress and high Tj results in the source-side degradation. To verify that high VDS is indeed not the reason for the increase in gate current and forward gate bias is essential, we design another experiment where VDS was at 0 volt with positive stress on the gate increasing from 0.1 to 2.5 V. Under such stress, there is not channel current flowing and there is forward gate bias on both source and drain side. Permanent degradation: Significant IDmax degradation ΔVT > 0 Significant IDoff degradation

Time evolution of IDmax and IGoff Stress conditions: VDS,stress = 0 V, VGS,stress = 0.1 – 2.5 V in 0.1 V steps stress time = recovery time = 150 s; characterization every 15 s RT IDmax @ VGS = 2 V, VDS = 4 V IGoff @ VGS = -2 V, VDS = 0.1 V 1.7 V 2.3 V |IGoff| starts to increase from VGS,stress ~ 1.7 V  trap generation in AlN IDmax starts to severely degrade from VGS,stress ~ 2.3 V  gate sinking

Time evolution of IGstress Stress conditions: VDS,stress = 0 V, VGS,stress = 0.1 – 2.5 V in 0.1 V steps stress time = recovery time = 150 s; characterization every 15 s RT 2.3 V IGstress increase becomes significant for VGS,stress ≥ 2.3 V

Gate current degradation After thermal detrapping, gate current degradation: IG After stress IS, ID IG IS, ID Before stress VDS=0 Symmetric degradation: IS ≈ ID ≈ IG/2 Reproduced degradation signature of high-VDS-high-ID stress: high forward VG leads to increase in IG

HRTEM of stressed device drain side Stressed device source side Gate metal Gate metal Gate metal passivation InAlN AlN InAlN GaN GaN Disordered region in GaN channel at gate edge on drain side Disordered region in GaN channel at gate edge on source side

Conclusions Permanent degradation after High-VDS-high-ID stress: IGoff   Defect formation in AlN barrier on source side ΔVT > 0, IDmax   Gate sinking Affects source side Positive gate stress: Reproduced degradation signature of high-VDS-high-ID stress: IGoff  , ΔVT > 0, IDmax  IS ~ ID ~ IG/2  Symmetric degradation on source and drain side

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