Day 17: October 8, 2014 Performance: Gates ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 17: October 8, 2014 Performance: Gates Penn ESE370 Fall2014 -- DeHon

First Order Delay t = R0C0 = C0/I0 Previously: R0 = Resistance of minimum size NMOS device I0 = Ids of minimum size NMOS device C0 = gate capacitance of minimum size NMOS device Rdrive = R0/Wn Idrive = WI0 Cg = WC0 Technology independent relative delay t = R0C0 = C0/I0 Large fanout – drive in stages Penn ESE370 Fall2014 -- DeHon

Today Delay in Gates Data Dependent Delay Large Fanin Do everything for two cases: Rp0=Rn0 and Rp0=2Rn0 Penn ESE370 Fall2014 -- DeHon

Gates Penn ESE370 Fall2014 -- DeHon

Data Dependent Delay Resistance depends on input values delay depends on input data t-delays assuming minsize? assume 2C0 load Penn ESE370 Fall2014 -- DeHon

How Size How size to equalize worst-case rise/fall times for Rdrive=R0/2? Penn ESE370 Fall2014 -- DeHon

Series Transistors Penn ESE370 Fall2014 -- DeHon

How Size How size for equal rise/fall for Rdrive=R0/2? Penn ESE370 Fall2014 -- DeHon

Input Load Input capacitance per input in each case? Penn ESE370 Fall2014 -- DeHon

Observe Ratio of Input Load Capacitance to Output Drive Strength: CILoad/Ids Differs with gate function Some gates give more drive per capacitive load we pay When Ids differ at same W Penn ESE370 Fall2014 -- DeHon

How Size Size equalize rise/fall times Rdrive=R0/2? Penn ESE370 Fall2014 -- DeHon

Increasing Fanin What happens to input capacitance as fanin (k) increases Keeping output drive the same E.g. Rdrive=R0/2 k-input nand gate has what input capacitance? Penn ESE370 Fall2014 -- DeHon

Fanin Conclude: gates slow down with fanin Less drive per input capacitance Penn ESE370 Fall2014 -- DeHon

Which is Fastest? nand32 nand4-inv-nand4-inv-nand2 (nand2-inv)4-nand2 Rn0=Rp0 case only nand32 nand4-inv-nand4-inv-nand2 (nand2-inv)4-nand2 Penn ESE370 Fall2014 -- DeHon

Lesson Large gates are slow / inefficient High capacitive load / drive strength Small gates can be inefficient Need many stages Staging over moderate size gates minimizes delay Exact size will be technology dependent Penn ESE370 Fall2014 -- DeHon

Delay of each implementation? Penn ESE370 Fall2014 -- DeHon

Take Away? Penn ESE370 Fall2014 -- DeHon

Ideas First order reason in t=R0C0 units Gates have different efficiencies Drive strength per unit input capacitance Without velocity saturation Reason to prefer nand over nor With velocity saturation (short term), nands and nors are similar efficiency Large fanin and fanout slow gates Decompose into stages …but not too much Penn ESE370 Fall2014 -- DeHon

Subversive Innovation Admin HW 6 is out Friday – Fall Break Back on Monday Tuesday 11am Talk by Herman Schmit Subversive Innovation Penn ESE370 Fall2014 -- DeHon