Dylan Lang Dylan.Lang@Samtec.com VITA 57.4 FMC+ Tutorial Dylan Lang Dylan.Lang@Samtec.com.

Slides:



Advertisements
Similar presentations
18 July 2001 Work In Progress – Not for Publication 2001 ITRS Test Chapter ITRS Test ITWG Mike Rodgers Don Edenfeld.
Advertisements

Flexible I/O in a Rigid World
Use of COTS Drop-in Replacement Designs to Solve Obsolescence of Electronic Components in Military Systems Willow Ridge Loop Orlando, FL
StackPC Stackable Computers
Sales Presentation November 2010
A reconfigurable system featuring dynamically extensible embedded microprocessor, FPGA, and customizable I/O Borgatti, M. Lertora, F. Foret, B. Cali, L.
BHEL – Electronics Division, Bangalore
Overview of VITA57 - FMC Denis Smetana
1 Design of the Front End Readout Board for TORCH Detector 10, June 2010.
Development of an ATCA IPMI Controller Mezzanine Board to be used in the ATCA developments for the ATLAS Liquid Argon upgrade Nicolas Dumont Dayot, LAPP.
Collection of information about the Hardware and firmware upload within the PSB rf system A. Blas FMC WG 20/01/ Topic of the meeting: make sure that.
General FPGA Architecture Field Programmable Gate Array.
HARDWARE OPAL-RT MARC PASTOR Real-Time 2009 Montreal, Quebec, Canada.
Wir schaffen Wissen – heute für morgen 24 August 2015PSI,24 August 2015PSI, Paul Scherrer Institut Status WP 8.2 RF Low Level Electronic Manuel Brönnimann.
HomeGate Backplane Solutions Brian Von Herzen, Ph.D. Xilinx Consultant June 21, 2004 ISO/IEC JTC1 SC25/WG1 N June 2004 (Von Herzen,
Personal Computer Hard Drive ATA Interface
Ross Brennan On the Introduction of Reconfigurable Hardware into Computer Architecture Education Ross Brennan
Electronics for PS and LHC transformers Grzegorz Kasprowicz Supervisor: David Belohrad AB-BDI-PI Technical student report.
Intorduction to Lumentis
Rapid prototyping platforms. Giving you the freedom to design solutions Providing Adopting Technology Adopting Technology to Process the Future.
XFEL The European X-Ray Laser Project X-Ray Free-Electron Laser Dariusz Makowski, Technical University of Łódź LLRF review, DESY, 3-4 December 2007 Advanced.
VPX Cover Overview and Update “VPX, Open VPX, and VPX REDI ” are trademarks of VITA.
Hardware proposal for the L2  trigger system detailed description of the architecture mechanical considerations components consideration electro-magnetic.
Development of Programmable Architecture for Base-Band Processing S. Leung, A. Postula, Univ. of Queensland, Australia A. Hemani, Royal Institute of Tech.,
Testing of ABC  Not to scale! 100nF Edge Sensor wired to A9, A10 ? ABC nF NB graphic is not an exact match with “ABC_Pads_V5.2.pdf”
1 COMPUTER ARCHITECTURE (for Erasmus students) Assoc.Prof. Stasys Maciulevičius Computer Dept.
XLV INTERNATIONAL WINTER MEETING ON NUCLEAR PHYSICS Tiago Pérez II Physikalisches Institut For the PANDA collaboration FPGA Compute node for the PANDA.
Photonic Components Rob Johnson Standards Engineering Manager 10th July 2002 Rob Johnson Standards Engineering Manager 10th July 2002.
Evaluation of Emerging Parallel Optical Link Technology for High Energy Physics John Chramowicz, Simon Kwan, Alan Prosser, Melissa Winchell Fermi National.
Rutherford Appleton Laboratory September 1999Fifth Workshop on Electronics for LHC Presented by S. Quinton.
Computer Organization IS F242. Course Objective It aims at understanding and appreciating the computing system’s functional components, their characteristics,
AMC-based Upgrade of Compute Node Hao XU Trigger group of IHEP, Beijing PANDA DAQT and FEE Workshop, Rauischholzhausen Castle April 2010.
Native Command Queuing (NCQ). NCQ is used to improve the hard disc performance by re-ordering the commands send by the computer to the hard disc drive.
E2800 Marco Deveronico All Flash or Hybrid system
WELCOME.
Serial I/O ADCs/DACs : The Next Giant Leap in Mixed-Signal for Space
Summary Remaining Challenges The Future Messages to Take Home.
Flexible I/O in a Rigid World
The SLAC Instrumentation and Control Platform
Test Boards Design for LTDB
AMC13 T1 Rev 2 Preliminary Design Review E. Hazen Boston University
HyperTransport™ Technology I/O Link
PRESS RELEASE Mid-Voltage Power MOSFETs in PQFN Package Utilizing Copper Clip Technology DATA SHEETS HI-RES GRAPHIC The new power MOSFETs featuring IR’s.
Direct Attached Storage and Introduction to SCSI
Large Area Endplate Prototype for the LC TPC
ROACH3 Introduction Alec Rust SKA-SA 1 1.
GTK-TO readout interface status
uTCA A Common Hardware Platform for CMS Trigger Upgrades
Architecture & Organization 1
FMC adapter status Luis Miguel Jara Casas 5/09/2017.
MicroTCA Common Platform For CMS Working Group
TPC Large Prototype Toward 7 Micromegas modules
Direct Attached Storage and Introduction to SCSI
Dr. Jeffrey M. Harris Director of Research and System Architecture
Programmable Logic Controllers (PLCs) An Overview.
ANSI/VITA 74 also known as
Front-end electronic system for large area photomultipliers readout
Comments on OCP Mezz v3 & Connector/Pinout Proposal
Architecture & Organization 1
XC4000E Series Xilinx XC4000 Series Architecture 8/98
A Digital Signal Prophecy The past, present and future of programmable DSP and the effects on high performance applications Continuing technology enhancements.
Presented by: ANDREW COOK, Chief Engineer, CEO
NetStream Diplo System Configuration
XC9500XL New 3.3v ISP CPLDs.
XILINX CPLDs The Total ISP Solution
The performance requirements for DSP applications continue to grow and the traditional solutions do not adequately address this new challenge Paradigm.
I/O BUSES.
I-Kang Fu, Paul Cheng, MediaTek
OCP Engineering Workshop Rack & Power, Advanced Cooling Solutions, Data Center Facility
Course Code 114 Introduction to Computer Science
Presentation transcript:

Dylan Lang Dylan.Lang@Samtec.com VITA 57.4 FMC+ Tutorial Dylan Lang Dylan.Lang@Samtec.com

Fmc+ abstract Backwards compatibility and expanded user I/O: FMC+ extends FMC’s performance and modularity Optical devices, serial memory, high-speed ADCs and DACs have necessitated additional Gigabit serial interfaces at speeds approaching 32 Gbps Original FMC Standard approaching 10-year anniversary since its inception, modular form factor still widely used, however, data rate needs to increase Modular approach to standard form factor allows for features such as AMC compatibility Next generation FPGA mezzanine allows for compatibility with latest high performance serial devices

What is fmc+? FMC+ is a Standard expanding the performance of FMC Expanded performance achieved using optimized pin mapping within the FMC+ connector Faster data rates, additional I/O, and backwards compatibility FMC+ module designed for deployment in a wide variety of applications Most common fields are FPGA development and VITA-based hardware systems like VPX Standard defines both air cooled as well as ruggedized conduction cooled versions Up to triple width modules are specified to facilitate applications requiring additional carrier card bandwidth, greater space on the front panel, or a larger PCB area. New high-speed connector set provides high performance computing from the mezzanine I/O to the FPGA on the carrier card FMC+ minimizes design time and creates a faster time-to-market

The story behind fmc+ Field Programmable Gate Array (FPGA) technology has proven to be invaluable to embedded designers for many years. Aid in de-risking designs by allowing engineers to modify their logic after silicon is on the board. This allows for more efficient prototyping and a faster time to market. Such diverse flexibility proved to limit demands of end users for a specific configuration. This was especially true in the case of COTS developers. A modular approach to a standardized form factor was driven through VITA. This became FMC, was ratified July 2008. Increased data rates and fundamentals of Moore’s Law demanded an interface that could handle improved performance. FMC+ Technical Work Group founded in 2014. Standard ratified and published by ANSI in July 2018.

Fmc+ signals Parameter FMC (VITA 57.1-2010) FMC+/HSPC (VITA57.4) FMC+/HSPCe (VITA57.4) Number of DIFF/SE I/O 80/160 M2C Clocks (DIFF) 2 Bi-Dir clocks (DIFF) SYNC M2C+C2M (DIFF) - 1+1 REFCLK M2C+C2M (DIFF) Multi-gigabit transceivers (interfaces) 10 24 32 Gigabit reference clocks 6 8 Max transceiver data rate 10Gbps 28Gbps I2C EEPROM capacity 2Kb (256x8) 2Kb (256x8) 32Kb+ (4K+ x8) Max Icc for 3P3VAUX power 20mA 100mA Max Single-width FMC module size (number of regions) (5.2+71.3+7.5) x 66mm (3 regions) (5.2+73.3+5.5) x 66mm (3 regions) or (5.2+73.3+5.5+10) x 66mm (4 regions) (5.2+73.3+5.5+10) x 66mm (4 regions) Max power 10W GA + JTAG + PowerGood + InstallID pins 2+5+2+1 2+5+2+2 2+5+2+3 Reserved pins 1 4 7 Connector pins (number of connectors) 10x40 (1) 14x40 (1) 14x40 + 4x20 (2)

Fmc+ connector FMC+ defines Samtec SeaRay HSPC (High Serial Pin Count) connector 14x40 configuration yielding 560 pins Increases multi-gigabit interfaces from 10 to 24 MGTs Multi-gigabit interface data rates up to 28Gbaud in each direction

Optional extension connector FMC+ also specifies an optional HSPCe (High Serial Pin Count extension) connector 4x20 array yielding an additional 80 pins Supports up to 8 additional multi-gigabit interfaces Utilizing both HSPC and HSPCe enables support of 32 multi-gigabit interfaces with up to 896 Gbps over 32 channels

FMC+ HSPC pinout

FMC+ HSPCe pinout

Fmc+ regions Regions 1 & 2 – Present on air-cooled carrier cards HSPC Connector HSPCe Connector Regions 1 & 2 – Present on air-cooled carrier cards Regions 2 & 3 - Present on ruggedized conduction cooled carrier cards Regions 1-3 – Present on ruggedized conduction cooled carrier cards needing Region 1 Regions 1-4 – Present when the optional HSPCe connector area is needed IO Area 31 mm x 50 mm Conduction Cooled Thermal Interface

Backwards compatibility with fmc Mechanically and electrically, FMC+ carriers are backwards compatible with FMC mezzanines 10x40 male FMC connector accepted by 14x40 female FMC+ connector Allows for greater flexibility and support of legacy designs Provides speeds of up to 10Gbps 10x40 FMC HPC Male 14x40 FMC+ HSPC Female

FMC+/AMC Carrier compatibility FMC+ defines two stack heights, 8.5mm and 10mm, which can be applied to VITA and AMC applications VITA applications allow for a minimum stack height of 8.5mm and a maximum of 10mm To accommodate AMC applications, clearance areas at the front and rear ends of Side 2 of the mezzanine have been lowered

ecosystem Expanding Ecosystem FMC Community FMC+ primarily adopted by two parties: FPGA Developers and VITA hardware FMC+ technologies expanding beyond ADC/DAC Optical, RF, and DSP configurations being released or in development Gaining deeper interest in COTS market New FMC+ Community being formed, to include discussions regarding marketing, technical advancements, and product development Any parties interested in FMC/FMC+ should apply (vita.com/fmc) Abaco Systems Alpha Data Parallel Systems Annapolis Micro Systems, Inc ApisSys SAS Atrenne Computing Solutions BittWare, Inc. Curtiss-Wright Faster Technology Intel Corporation Interface Concept Mercury Systems, Inc. Nutaq Pentek, Inc. Parsec ReFLEX CES Samtec Talent Technology Co., Ltd. TechwaY Tokyo Electron Device Ltd. VadaTech Inc. Xilinx

Working group history Initial work started in 2015 ANSI Ratification in 2018 To update in 2023 per ANSI specification New dot specifications underway VITA 57.5 – Physical Tools to Aid in FMC+ Development To include cable assemblies, loopback cards, and standoffs VITA 57.1/57.4 Synergy Currently, VITA 57.1 is undergoing its 5-year ANSI revision Improved Figures and signal context to improve agreement between VITA 57.1 FMC/VITA 57.4 FMC+ specifications Bundled as one Standard on vita.com

Vita 57.5 physical tools to aid in FMC+ development Technical Work Group to begin late July/early August 2018 Tools to include: Loopback Cards – development tool for FPGA designers looking to test and confirm signal integrity between mezzanines and carriers Jumper Cables – appropriate for users looking to extend FMC+ signals over distances greater than the defined 8.5mm and 10mm stack heights Jackscrew Standoffs – useful to ease separation of FMC configurations with high-pin counts (i.e. double and triple wide FMC+ cards utilizing HSPCe)

summary FMC+ poised to see continued growth within FPGA and VITA communities With additional I/O and higher data rates, FMC+ provides even greater flexibility for configurable FPGA I/O New and existing adoptions of FMC+ include radio, optics, and advanced sensor/radar applications With the addition of VITA 57.5 application notes, FMC family of standards will continue to prove advantageous: Leading to a more rapid design process Offering a cost-effective approach Supporting more bandwidth and channels

Thank you