Automatic Test Generation for Combinational Circuits Sungho Kang Yonsei University

Outline Introduction Faults and Fault Models Automatic Test Generation Redundancy Removal

Introduction Quality of Test Y : Yield DL: Defect Level d : defect coverage DL = 1 - Y 1-d Consider a 0.5 yield process To achieve 0.01 defect level, 99% coverage is required To achieve 80% coverage, 0.2 defect level

Faults and Fault Models Represent the effect of physical defects on the behavior of the modeled system Advantages of Modeling The problem of fault analysis is a logical rather than physical problem Complexity is reduced Technology-independent Tests derived for logical faults are valid for physical faults Requirements Accuracy Tractability

Fault Models Gate Level Faults Transistor Level Faults Delay Faults Stuck-at Short between signal and ground or power Bridging Short between two signals Transistor Level Faults Short Connecting points not intended to be connected Open(break) Breaking a connection Stuck-on (stuck-short) Stuck-open (stuck-off) Delay Faults Temporary Faults

Stuck-at Fault Models Stuck-at-1 Stuck-at-0 Faults Stuck-at-1 Faulty line permanently set to 1 Stuck-at-0 Faulty line permanently set to 0 Fault can be at an input or output of a gate Single Stuck at Faults The number of stuck at faults is 2N where N is the number of fault sites Reasons why widely used Represents many different physical faults Independent of technology Tests that detect stuck faults detect other faults well The number of faults is small Can be used to model other type of faults

Stuck-at Fault Models Multiple Stuck at Faults 2 or more lines have faults but not necessarily the same value The number of faults is 3N-1 A multiple faults is unidirectional if all of its constituent faults are either s-a-0 or s-a-1 but not both simultaneously

Fault Equivalence Faults Two faults f and g are said to be functionally equivalent iff Zf(x) = Zg(x) for all x A test t is said to distinguish between two faults f and g if Zf(t)  Zg(t) Consider one representative fault from every equivalence class Set of all tests that distinguishes between f and g is Zf(x)  Zg(x) For n input gate, 2(n+1) single stuck faults All input s-a-C faults and output s-a-(CI) are equivalent C : controlling value I : inversion Consider only (n+2) faults

Fault Equivalence Fault Equivalence Collapsing Faults Fault Equivalence Collapsing The main goal of fault collapsing is to reduce the total number of faults required to simulate by grouping all the indistinguishable faults into several fault classes and only simulating one from each class Two faults f and g are functionally equivalent under a test set T iff Zf(T) = Zg(T) for every test t  T Gate Collapsing Signal Collapsing Extended Collapsing

Fault Collapsing Example x s-a-0, y s-a-0, z s-a-0 x s-a-1 y s-a-1 Faults Example x s-a-0, y s-a-0, z s-a-0 x s-a-1 y s-a-1 z s-a-1

Fault Collapsing Example Faults Example X1 X2 Z A/0 B/0 C/0 D/0 E/0 F/0 A/1 B/1 C/1 D/1 E/1 F/1 0 0 1 1 1 1 1 1 0 0 0 1 1 1 1 0 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 1 1 1 1 0 0 1 0 1 1 1 1 0 1

Fault Collapsing Example 26 faults {A/1,E/1,G/1} {A/0} {E/0} {G/0} {B/0,C/1} {B/1,C/0} {F/1,D/1,I/0,J/0,L/0,H/1} {F/0} {D/0} {I/1} {H/0,J/1} {L/1,K/1,M/1} {K/0} {M/0} 14 faults

Fault Equivalence Sequential Circuits Faults Sequential Circuits Two faults f and g are strongly functionally equivalent iff the corresponding sequential circuits Nf and Ng have equivalent state tables Two faults f and g are functionally equivalent iff Rf(qIf,T) = Rg(qIg,T) for any T

Test Pattern Generation ATPG Test generation Manual generation Pseudo random generation Algorithmic (or deterministic) test generation Automatic Test Pattern Generation (ATPG) Calculate the set of test patterns from a description of the logic network and a set of assumptions called fault models

ATPG Result of ATPG Cost of ATPG Quality of the generated tests Find a test pattern Redundant fault Run out of time/memory (Aborted fault) Cost of ATPG Low CPU time Quality of the generated tests High fault coverage Cost of Applying Test Small number of tests Fault Coverage # of detected faults / # of faults # of detected faults / (# of faults - # of redundant faults) (# of detected faults + # of redundant faults) / # of faults

Definition Fault Excitation Fault Propagation ATPG Fault Excitation The process of finding a sufficient set of PI values to cause the fault site in the good circuit to have a value opposite to the faulty value Fault Propagation The process of moving the effect of a fault closer to a PO

Definition Single Fault Assumption Implication ATPG Single Fault Assumption The assumption that one and only one fault is present in a given circuit at a time Implication The process of determining the unique values implied by already assigned values The process can cause both forward and backward assignment of values

Definition Reconvergent fanout Line Justification ATPG Reconvergent fanout A fanout node, two or more of whose branches eventually are used as inputs to the same element The element at which the branch reconverge is called the point of reconvergence Line Justification The process of finding a set of PI values which cause the line to achieve the desired value Essentially the same as backdrive with conflict resolution

Definition Backtracking ATPG Backtracking Retracing in the search space to resolve the conflict by trying alternate assignments at previously assigned nodes Should store previously determined values

Definition A test cannot detect both s-a-0 and s-a-1 ATPG A test cannot detect both s-a-0 and s-a-1 Reconvergent fanout free circuits are easy to generate tests Redundant fault

General Outline of ATPG Choose a fault if imply-and-check() = FAILURE return FAILURE if fault effect at PO and all lines are justified return SUCCESS if no fault effect can be propagated to a PO select an unsolved problem repeat select one untried way to solve it if solve( ) = success until all ways to solve it have been tried

ATPG Example ATPG F output s-a-0

ATPG Example ATPG G output s-a-1

ATPG Example ATPG H s-a-1

D Algorithm ATPG Introduce D and D’

D Algorithm : Example G s-a-1 To generate 0 at the output of G A=B=C=1 ATPG G s-a-1 To generate 0 at the output of G A=B=C=1 To propagate through J output of F=1 It implies A=B=0 Contradicts!!!

PODEM Path Oriented DEcision Making Search space on PIs ATPG Path Oriented DEcision Making Search space on PIs Implicit space enumeration Algorithm PODEM() if (Error at PO) return SUCCESS if (test not possible) return FAILURE get an objective backtrace the objective to PI imply the PI value if PODEM() == SUCCESS imply PI with X value assume target fault is I s-a-v objective() if ( the value of I is X ) return (I, v’) select a gate(G) from the D frontier select an input j of G with value X c = controlling value of G return ( j, c’)

PODEM Example ATPG a s-a-0 : using PODEM

PODEM Example ATPG Continued Decision Tree

FAN Assume that we want to set J=0 ATPG Assume that we want to set J=0 Assume that with PI assignments previously made, setting J=0 causes D frontier empty Failure

Multiple Backtrace ATPG Determines an assignment that is likely either to contribute achieving a subset of the original objectives or to show that some subset of the original objectives cannot be simultaneously achieved Different objectives are backtracked to its same stem with conflicting at its branches Multiple backtrace stops backtracing when a stem is reached and keeps track of the number of times a 0 and 1 have been requested on the stem

X Path Check X path check ATPG X path check Let s be a signal on the fault sensitization path If s has 0 or 1, the fault cannot be propagated Check the value using forward implication

Dominator ATPG A signal y is said to dominate a signal x if all directed paths from x to the POs pass through y Dominator The set of signal that dominate signal x The fault effect should pass through dominators Off-path inputs of dominators are assigned noncontrolling values to propagate fault effect Example Dominators of signal C : G2 and G5 Thus D=0 and J=1

Static learning ATPG To assign a logic value to a certain signal of the circuit, perform This is done for all signals of the circuit for both logic value 0 and 1 Example B=1 => F=1 F=0 => B=0

Fault Simulation ATPG

2 Phase ATPG Random + Deterministic while an exit condition happens get a vector fault simulate the vector if the vector detects faults add the vector to the test set discard the faults for all remaining faults select a fault generate a vector if successful add the vector in the test set

Redundancy Identification Redundancy Removal Test Covering and Fault Dominance f : Z1 s-a-1 g : Y1 s-a-1  Tg = 10 Tg detects f, but f does not dominate g f dominates g if f and g are functionally equivalent under Tg But test covering does not require such functional equivalence If f dominates g, then f also test covers g But converse is not necessarily true

Redundancy Identification Redundancy Removal Let S be a stem with fanout branch (S1, S2, ... , Sn) If Si is nonreconvergent, then S s-a-v test covers Si s-a-v If Si and Sj reconverge only with equal inversion parities then S s-a-v test covers both Si s-a-v and Sj s-a-v If a stem is redundant, then its nonreconvergent fanout branches and fanout branches reconvergent only with equal inversion parity are also redundant

Redundancy Removal Redundancy Removal Removal of F s-a-0

Redundancy Removal Redundancy Removal There are circuits where removal of a redundant fault exposes another redundant fault There are circuits where removal of one redundancy makes the circuit slower 2-bit carry skip adder