Lecture 13 PicoBlaze I/O & Interrupt Interface ECE 448 – FPGA and ASIC Design with VHDL

ECE 448 – FPGA and ASIC Design with VHDL Required reading P. Chu, FPGA Prototyping by VHDL Examples Chapter 16, PicoBlaze I/O Interface Chapter 17, PicoBlaze Interrupt Interface ECE 448 – FPGA and ASIC Design with VHDL

Syntax and Terminology Syntax Example Definition sX KK PORT(KK) PORT((sX)) RAM(KK) s7 ab PORT(2) PORT((s1)) RAM(4) Value at register 7 Value ab (in hex) Input value from port 2 Input value from the port specified by register s1 Value from the RAM location 4

Addressing modes Immediate mode SUB s7, 07 s7 – 07  s7 ADDCY s2, 08 s2 + 08 + C  s2 Immediate mode SUB s7, 07 ADDCY s2, 08 Direct mode ADD sa, sf INPUT s5, 2a sa + sf  sa PORT(2a)  s5 Indirect mode STORE s3, (sa) INPUT s9, (s2) s3  RAM((sa)) PORT((s2))  s9

Output Decoding of Four Output Registers ECE 448 – FPGA and ASIC Design with VHDL

− − − − Output Instructions C Z OUTPUT sX, KK DIR PORT(KK) <= sX OUTPUT sX, (sY) PORT((sY)) <= sX − − DIR IND − −

Timing Diagram of an Output Instruction ECE 448 – FPGA and ASIC Design with VHDL

Truth Table of a Decoding Circuit ECE 448 – FPGA and ASIC Design with VHDL

− − − − Input Instructions C Z INPUT sX, KK DIR sX <= PORT(KK) INPUT sX, (sY) sX <= PORT((sY)) − − DIR IND − −

Block Diagram of Four Continuous-Access Ports ECE 448 – FPGA and ASIC Design with VHDL

Timing Diagram of an Input Instruction ECE 448 – FPGA and ASIC Design with VHDL

Block Diagram of Four Single-Access Ports ECE 448 – FPGA and ASIC Design with VHDL

ECE 448 – FPGA and ASIC Design with VHDL FIFO Interface clk rst clk rst FIFO din dout 8 8 full empty write read ECE 448 – FPGA and ASIC Design with VHDL

Operation of the First-Word Fall-Through FIFO ECE 448 – FPGA and ASIC Design with VHDL

Operation of the “Standard” FIFO B C D −−−−− ECE 448 – FPGA and ASIC Design with VHDL

ECE 448 – FPGA and ASIC Design with VHDL Interrupt Flow ECE 448 – FPGA and ASIC Design with VHDL

Timing Diagram of an Interrupt Event ECE 448 – FPGA and ASIC Design with VHDL

ECE 448 – FPGA and ASIC Design with VHDL

Interrupt Related Instructions RETURNI ENABLE PC <= STACK[TOS] ; TOS <= TOS – 1; I <= 1; C<= PRESERVED C; Z<= PRESERVED Z RETURNI DISABLE I <= 0; C<= PRESERVED C; Z<= PRESERVED Z ENABLE INTERRUPT I <=1; DISABLE INTERRUPT I <=0;

Interrupt Interface with a Single Event ECE 448 – FPGA and ASIC Design with VHDL

Interrupt Interface with Two Requests ECE 448 – FPGA and ASIC Design with VHDL

Time-Multiplexed Seven Segment Display ECE 448 – FPGA and ASIC Design with VHDL

Block Diagram of the Hexadecimal Time-Multiplexing Circuit ECE 448 – FPGA and ASIC Design with VHDL

ECE 448 – FPGA and ASIC Design with VHDL Hexadecimal Multiplexing Circuit Based on PicoBlaze and mod-500 Counter ECE 448 – FPGA and ASIC Design with VHDL