ESE 437: Sensors and Instrumentation Introduction to Verilog

Hardware Description Language

Verilog HDL - Module

Verilog HDL - Module

Verilog HDL - Module

Verilog HDL - Module

Verilog HDL - Module

Verilog HDL - Constant

Verilog HDL – Parameters

Verilog HDL – Parameters

Non-blocking Assignments

Blocking Assignments

iClick Question In the following example, what is the values of register D? A) D=A B) D=B C) D=C

Verilog HDL – Operators

Verilog HDL – Operators

Verilog HDL – Operators

Verilog HDL – Operators

Verilog HDL – Operators

Verilog HDL – Assignments

Verilog Example Implement a circular shift Bit_0 will get the value from bit_7 Bit_1 will get the value from bit_2 Bit_2 will get the value from bit_3… module circular_shift (input_reg, output_reg,clk) output [7:0] output_reg; input [7:0] input_reg; input clk; always @(posedge clk) output_reg[1:7] = input_reg[0:6]; output_reg[0] = inout_reg[7]; endmodule

Verilog Example Implement a circular shift Bit_0 will get the value from bit_7 Bit_1 will get the value from bit_2 Bit_2 will get the value from bit_3… module circular_shift (input_reg, output_reg,clk) output [7:0] output_reg; input [7:0] input_reg; input clk; always @(posedge clk) output_reg = {input_reg[6:0], inout_reg[7]}; endmodule

Verilog HDL – Assignments

Verilog HDL – Always

Verilog HDL – Always

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Parallel load register

Verilog HDL – If Instruction

Verilog HDL Example

Verilog HDL – Case Instruction

Verilog HDL Example

Verilog HDL – Module Instantiation

Verilog HDL – Module Instantiation

Verilog HDL – Examples

Verilog HDL – Examples

Verilog HDL – Example

Verilog HDL – Example

Verilog HDL – Example

Verilog HDL – Example

Verilog HDL – Example // state declarizations reg [3:0] state; localparam STATE_INIT = 3'd0; localparam STATE_TX = 3'd1; localparam STATE_RX = 3'd2; localparam STATE_CALC = 3'd3; localparam STATE_IDLE = 3'd4; always @ (posedge clock) begin case(state) begin STATE_INIT : begin state <= STATE_TX; end STATE_TX : begin if (conditional) begin state <= STATE_RX; end else begin state <= STATE_TX; end end STATE_RX : begin // do something else end STATE_CALC : begin // do something else end endcase end

Verilog HDL Example