Design of benchmark circuit s5378 for reduced scan mode activity

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Presentation transcript:

Design of benchmark circuit s5378 for reduced scan mode activity Nelson Sunwoo

objective Modify s5378 to full scan design Modify scan flip flops to prevent switching in combination logic Compare average power consumption of original and enhanced design

Problem with testing Scan shift causes redundant switching in combination logic. Power dissipation during the test mode is up to three times higher than normal mode.

Original circuit . . . Scan Flip Flop SO D mux DFF 1 Q SI SE Combinational logic Scan flip- flops Primary inputs outputs SI SO SE D Q Scan Flip Flop Scan flip- flops Scan flip- flops DFF mux SE SI D Q SO 1 Scan flip-flop . . .

Original circuit simulation

Modified circuit

Modified circuit simulation

Power analysis technology: TSMC 0.18um Vdd: 1.8V clock speed: 1GHz 1000 random vector sets - inputs (0.5 activity) - Scan in (random)

simulation

result Original design Modified design Power reduction Average Power 52.559mW 36.252mW 31 %

reference S. Gerstendrfer and H. J. Wunderlich, Minimized Power Consumption for Scan-based BIST, International Test Conference, 1999, pp 77-84.