Direct Memory Access Disk and Network transfers: awkward timing: Latency: milliseconds Transfer rate: megabytes per second Too fast for interrupts Too slow for polling (cope with latency?) 5 December 2018 CS2051 Lecture 8

DMA Interface Memory CPU DMA controller DMA Cycle Steal CPU: Disk Address Memory Address Count Command Status Memory DMA Cycle Steal CPU: fetch instruction decode fetch operand operate CPU 5 December 2018 CS2051 Lecture 8

Example: DMA Transfer from disk Process (running) … fread(…) /* will free CPU? */ //(non-blocking I/O?) Device Driver told to transfer data from disk to memory buffer CPU (running other processes) … ISR Disk Controller Initiates transfer Sends bytes to DMA controller DMA Controller Transfers bytes to memory buffer When completed, interrupts the CPU Interrupt 5 December 2018 CS2051 Lecture 8

Memory Mapped I/O Interface may appear as memory location e.g. write to disk interface control register initiates transfer e.g. write pixels to frame buffer - changes appearance of screen NB: protection issues 5 December 2018 CS2051 Lecture 8

Timers Usually generate interrupts for: Time of Day (real clock chip?) time slice for fair use of CPU alarm clock service for applications monitoring/profiling Application OS Network & Device timeouts Typically 50-1000 interrupts per sec 5 December 2018 CS2051 Lecture 8

Exceptions e.g. Division by zero Odd address accessed Invalid memory address used Undefined instruction executed Similar to interrupts (save PC/PSR; set PRIV, goto handler) via vector table Synchronous to current running program 5 December 2018 CS2051 Lecture 8

How does Application enter OS? (user mode vs system mode) e.g. application wishes to delete file, or send network packet Why not by procedure call instruction? Use Trap or Software Interrupt instruction, causing exception Pass parameters? 5 December 2018 CS2051 Lecture 8

Summary Reading: Bacon 3.2, 3.3 (3.2.7 for information only) DMA: saves CPU time by controlling data transfer between I/O device and memory. Memory mapped I/O used to transfer data to and from a device (registers included) by allocating physical memory addresses to device interfaces. Interrupt mechanisms are used to handle a variety of exceptions “(with interrupts) the processor doesn’t waste its time looking for work: when there is something to be done, the work comes looking for the processor” Reading: Bacon 3.2, 3.3 (3.2.7 for information only) 5 December 2018 CS2051 Lecture 8