MCP Electronics Time resolution, costs

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Presentation transcript:

MCP Electronics Time resolution, costs

MCP signals simulation: 200ps rise time 400ps fall time Shot noise 50% Output noise 50% Signal/noise=30 Sampling frequency 10 - 100 GHz

MCP signals: 200ps rise time

Performance sensitivity to feature size 1 Input analog bandwidth limitations: - IO pads ESD protections Yes (RF diodes) + - Effective input signal load (R, L, C) No - Open switches parasitics Yes + 2 Sampling process - Switch resistance Yes + - Storage capacitance value No (kT/C limited) - Number of caps at a time No (constant ~ 4) - Aperture jitter Yes + - Dynamic range Yes Voltage supply dep .-

DLL’s Architecture (25ps sampling) 625 MHz clock in 16 cells 125ps 100ps 100ps 100ps 100ps 150ps 175ps 16 * 4 = 64 cells

Costs vs Sampling frequency Assuming sampling period proportionnal to feature size, scaled to 10GHz @ 250nm 90 130 250 180

Costs vs time resolution Assuming sampling period proportional to feature size scaled to 25mm2 design in 250nm 90 130 250 180