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Presentation transcript:

IHP Im Technologiepark Frankfurt (Oder) Germany IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved An Implementation Study on Fault Tolerant LEON-3 Processor System Z. Stamenković

IHP Innovations for High Performance MicroelectronicsSlide 2© All rights reserved Outline Radiation and fault tolerance System description Implementation details Test results Under way

IHP Innovations for High Performance MicroelectronicsSlide 3© All rights reserved Reliability Issues in Radiation Environments Single-event upset (SEU) A change of state caused by a charged particle strike to a sensitive volume in a microelectronic device Alpha particles (helium-4 nuclei) emitted by radioactive atoms found in packaging materials Thermal neutrons in certain device materials that are heavily doped with 10 B High-energy terrestrial cosmic rays (play a major role) SEU-induced latch-up A failure mechanism of CMOS integrated circuits characterized by excessive current due to parasitic PNPN paths

IHP Innovations for High Performance MicroelectronicsSlide 4© All rights reserved Fault Tolerance of LEON-3 Processor SEU tolerance by design (Gaisler Research) Triple-module-redundancy (TMR) on all flip-flops Three copies of a flip-flop Two of three voting on output Register file error-correction (up to 4 errors per 32-bit word) Cache RAM error-correction (up to 4 errors per tag or 32-bit word) Autonomous and software transparent error handling No timing impact due to error detection or correction Fault-tolerant memory controller Provides an Error Detection And Correction Unit (EDAC) Corrects one and detects two errors Not immune to SEU-induced latch-up (in present IHP technology)

IHP Innovations for High Performance MicroelectronicsSlide 5© All rights reserved LEON-3 Processor System LEON_3FT Core 8 Reg. Windows LEON_3FT Core 8 Reg. Windows FT Memory Controller FT Memory Controller 8 x GPIO GPIOEJTAG 2 kByte I- Cache 2 kByte I- Cache 2 kByte D- Cache 2 kByte D- Cache AHB APB 1 x 24bit Timer UART 0 EDAC SRAM FLASH Serial 0 Serial 1 UART 1 Bridge Scan Test FT Add-on Scan-I/F

IHP Innovations for High Performance MicroelectronicsSlide 6© All rights reserved Installation of the release Adaptation of the configuration tool (to include IHPs library) Implementation of data and instruction caches Logic synthesis of the design Implementation of scan chain Generation of the chip layout Simulation (functional, post-synthesis and post-layout net-list) Scan test vectors generation (ATPG) Scan test simulation Adaptation of testbenches EVCD test vectors generation Test specification Documentation Implementation Details

IHP Innovations for High Performance MicroelectronicsSlide 7© All rights reserved Chip Features

IHP Innovations for High Performance MicroelectronicsSlide 8© All rights reserved Test System (Gaisler Research) Target hardware consists of a small mezzanine with Fault Tolerant LEON-3 device mounted on a development board (Pender Electronic Design) Board communicates with a host system (a laptop PC) over one of the on-chip UARTs

IHP Innovations for High Performance MicroelectronicsSlide 9© All rights reserved Test Execution (Gaisler Research) Heavy-ion-error injection Chamber with the vacuum of mbar Californium (Cf-252) source Flux of 25 particles/s/cm 2 at the device surface for 3 hours Paranoia program makes a large number of calculations and registers any computational error or anomaly On-chip monitoring logic reported 281 effective SEU errors, of which 99% were corrected Cross-section for a memory RAM bit was measured to 7.2x10 -8 cm 2

IHP Innovations for High Performance MicroelectronicsSlide 10© All rights reserved Under Way Protection against SEU-induced latch-up